From 8e97b7a248403ca9e9b38a70997fdb8ff93dfe94 Mon Sep 17 00:00:00 2001 From: Andrea Mazzoleni Date: Sun, 14 Sep 2014 19:47:43 +0200 Subject: [PATCH] Adds proper detection for AVX2. --- cmdline/speed.c | 3 +-- raid/cpu.h | 28 ++++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/cmdline/speed.c b/cmdline/speed.c index e4867669..a2e83d05 100644 --- a/cmdline/speed.c +++ b/cmdline/speed.c @@ -122,12 +122,11 @@ void speed(int period) raid_cpu_info(vendor, &family, &model); - printf("CPU %s, family %u, model %u, flags%s%s%s%s%s%s%s%s%s\n", vendor, family, model, + printf("CPU %s, family %u, model %u, flags%s%s%s%s%s%s%s%s\n", vendor, family, model, raid_cpu_has_mmx() ? " mmx" : "", raid_cpu_has_sse2() ? " sse2" : "", raid_cpu_has_ssse3() ? " ssse3" : "", raid_cpu_has_sse42() ? " sse42" : "", - raid_cpu_has_avx() ? " avx" : "", raid_cpu_has_avx2() ? "avx2" : "", raid_cpu_has_slowmult() ? " slowmult" : "", raid_cpu_has_slowpshufb() ? " slowpshufb" : "", diff --git a/raid/cpu.h b/raid/cpu.h index 5511e916..164321f2 100644 --- a/raid/cpu.h +++ b/raid/cpu.h @@ -106,19 +106,43 @@ static inline int raid_cpu_has_sse42(void) return (reg[2] >> 20) & 1; } -static inline int raid_cpu_has_avx(void) +static inline int raid_cpu_has_xsavexrstor(void) { uint32_t reg[4]; raid_cpuid(1, 0, reg); - return (reg[2] >> 28) & 1; + return (reg[2] >> 27) & 1; +} + +static inline int raid_os_support_256bit_regs(void) +{ + uint32_t reg[4]; + + /* get the value of the Extended Control Register ecx=0 */ + asm volatile( + "xgetbv\n" + : "=a" (reg[0]), "=d" (reg[3]) + : "c" (0) + ); + + /* check if the OS save all the 256 bits registers */ + return (reg[0] & 0x6) == 0x6; } static inline int raid_cpu_has_avx2(void) { uint32_t reg[4]; + /* check if the CPU supports XSAVE and XRSTOR, and also XGETBV */ + if (!raid_cpu_has_xsavexrstor()) + return 0; + + /* check if the OS suports AVX2 registers */ + if (!raid_os_support_256bit_regs()) + return 0; + + /* now check for AVX2 support */ raid_cpuid(7, 0, reg); return (reg[1] >> 5) & 1;