mirror of
https://github.com/amadvance/snapraid.git
synced 2026-10-26 19:01:57 -04:00
Preliminary AVX2 support.
This commit is contained in:
Andrea Mazzoleni
parent
b32e3cdc03
commit
957db46f5b
7 changed files with 154 additions and 11 deletions
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@ -259,6 +259,10 @@ void speed(int period)
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printf("%8s", "ssse3");
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#ifdef CONFIG_X86_64
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printf("%8s", "ssse3e");
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#endif
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printf("%8s", "avx2");
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#ifdef CONFIG_X86_64
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printf("%8s", "avx2e");
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#endif
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#endif
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printf("\n");
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@ -293,6 +297,19 @@ void speed(int period)
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printf("%8"PRIu64, ds / dt);
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fflush(stdout);
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}
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printf("%8s", "");
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printf("%8s", "");
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printf("%8s", "");
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if (raid_cpu_has_avx2()) {
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SPEED_START {
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raid_gen1_avx2(nd, size, v);
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} SPEED_STOP
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printf("%8"PRIu64, ds / dt);
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fflush(stdout);
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}
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#endif
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printf("\n");
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@ -333,8 +350,22 @@ void speed(int period)
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printf("%8"PRIu64, ds / dt);
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fflush(stdout);
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#else
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printf("%8s", "");
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#endif
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}
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printf("%8s", "");
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printf("%8s", "");
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if (raid_cpu_has_avx2()) {
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SPEED_START {
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raid_gen2_avx2(nd, size, v);
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} SPEED_STOP
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printf("%8"PRIu64, ds / dt);
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fflush(stdout);
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}
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#endif
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printf("\n");
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@ -67,9 +67,11 @@ void raid_rec2of2_int8(int *id, int *ip, int nd, size_t size, void **vv);
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void raid_gen1_int32(int nd, size_t size, void **vv);
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void raid_gen1_int64(int nd, size_t size, void **vv);
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void raid_gen1_sse2(int nd, size_t size, void **vv);
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void raid_gen1_avx2(int nd, size_t size, void **vv);
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void raid_gen2_int32(int nd, size_t size, void **vv);
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void raid_gen2_int64(int nd, size_t size, void **vv);
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void raid_gen2_sse2(int nd, size_t size, void **vv);
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void raid_gen2_avx2(int nd, size_t size, void **vv);
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void raid_gen2_sse2ext(int nd, size_t size, void **vv);
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void raid_genz_int32(int nd, size_t size, void **vv);
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void raid_genz_int64(int nd, size_t size, void **vv);
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@ -79,6 +79,11 @@ void raid_init(void)
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raid_rec_ptr[4] = raid_recX_ssse3;
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raid_rec_ptr[5] = raid_recX_ssse3;
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}
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if (raid_cpu_has_avx2()) {
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raid_gen_ptr[0] = raid_gen1_avx2;
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raid_gen_ptr[1] = raid_gen2_avx2;
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}
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#endif
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/* set the default mode */
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@ -43,6 +43,8 @@ static struct raid_func {
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{ "ssse3", raid_rec1_ssse3 },
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{ "ssse3", raid_rec2_ssse3 },
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{ "ssse3", raid_recX_ssse3 },
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{ "avx2", raid_gen1_avx2 },
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{ "avx2", raid_gen2_avx2 },
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#endif
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#ifdef CONFIG_X86_64
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@ -309,6 +309,11 @@ int raid_test_par(int mode, int nd, size_t size)
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f[nf++] = raid_gen2_sse2ext;
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#endif
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}
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if (raid_cpu_has_avx2()) {
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f[nf++] = raid_gen1_avx2;
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f[nf++] = raid_gen2_avx2;
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}
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#endif
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if (mode == RAID_MODE_CAUCHY) {
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102
raid/x86.c
102
raid/x86.c
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@ -56,15 +56,54 @@ void raid_gen1_sse2(int nd, size_t size, void **vv)
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}
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#endif
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#ifdef CONFIG_X86
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/*
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* GEN1 (RAID5 with xor) AVX2 implementation
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*
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* Intentionally don't process more than 64 bytes because 64 is the typical
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* cache block, and processing 128 bytes doesn't increase performance, and in
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* some cases it even decreases it.
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*/
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void raid_gen1_avx2(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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raid_asm_begin();
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for (i = 0; i < size; i += 64) {
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (v[l][i]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (v[l][i+32]));
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for (d = l-1; d >= 0; --d) {
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asm volatile("vpxor %0,%%ymm0,%%ymm0" : : "m" (v[d][i]));
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asm volatile("vpxor %0,%%ymm2,%%ymm2" : : "m" (v[d][i+32]));
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}
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asm volatile("vmovntdq %%ymm0,%0" : "=m" (p[i]));
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[i+32]));
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}
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raid_asm_end();
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}
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#endif
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#ifdef CONFIG_X86
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static const struct gfconst16 {
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uint8_t poly[16];
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uint8_t low4[16];
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} gfconst16 __aligned(32) = {
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{ 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
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{ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
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0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f },
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} gfconst16 __aligned(32) = {
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{
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d
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},
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{
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0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
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0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f
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},
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};
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#endif
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@ -122,6 +161,59 @@ void raid_gen2_sse2(int nd, size_t size, void **vv)
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}
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#endif
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#ifdef CONFIG_X86
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/*
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* GEN2 (RAID6 with powers of 2) AVX2 implementation
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*/
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void raid_gen2_avx2(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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uint8_t *q;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd+1];
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raid_asm_begin();
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asm volatile("vbroadcasti128 %0, %%ymm7" : : "m" (gfconst16.poly[0]));
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asm volatile("vpxor %ymm6,%ymm6,%ymm6");
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for (i = 0; i < size; i += 64) {
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (v[l][i]));
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asm volatile("vmovdqa %0,%%ymm1" : : "m" (v[l][i+32]));
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asm volatile("vmovdqa %ymm0,%ymm2");
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asm volatile("vmovdqa %ymm1,%ymm3");
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for (d = l-1; d >= 0; --d) {
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asm volatile("vpcmpgtb %ymm2,%ymm6,%ymm4");
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asm volatile("vpcmpgtb %ymm3,%ymm6,%ymm5");
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asm volatile("vpaddb %ymm2,%ymm2,%ymm2");
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asm volatile("vpaddb %ymm3,%ymm3,%ymm3");
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asm volatile("vpand %ymm7,%ymm4,%ymm4");
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asm volatile("vpand %ymm7,%ymm5,%ymm5");
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asm volatile("vpxor %ymm4,%ymm2,%ymm2");
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asm volatile("vpxor %ymm5,%ymm3,%ymm3");
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asm volatile("vmovdqa %0,%%ymm4" : : "m" (v[d][i]));
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asm volatile("vmovdqa %0,%%ymm5" : : "m" (v[d][i+32]));
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asm volatile("vpxor %ymm4,%ymm0,%ymm0");
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asm volatile("vpxor %ymm5,%ymm1,%ymm1");
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asm volatile("vpxor %ymm4,%ymm2,%ymm2");
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asm volatile("vpxor %ymm5,%ymm3,%ymm3");
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}
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asm volatile("vmovntdq %%ymm0,%0" : "=m" (p[i]));
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asm volatile("vmovntdq %%ymm1,%0" : "=m" (p[i+32]));
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (q[i]));
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asm volatile("vmovntdq %%ymm3,%0" : "=m" (q[i+32]));
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}
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raid_asm_end();
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}
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#endif
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#ifdef CONFIG_X86_64
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/*
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* GEN2 (RAID6 with powers of 2) SSE2 implementation
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18
raid/x86z.c
18
raid/x86z.c
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@ -20,12 +20,18 @@ static const struct gfzconst16 {
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uint8_t half[16];
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uint8_t low7[16];
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} gfzconst16 __aligned(64) = {
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{ 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
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{ 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e,
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0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e },
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{ 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f }
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{
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
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0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d
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},
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{
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0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e,
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0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e, 0x8e
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},
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{
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f
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}
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};
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#endif
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