diff --git a/raid/internal.h b/raid/internal.h
index a1f95b7f..357bbd90 100644
--- a/raid/internal.h
+++ b/raid/internal.h
@@ -85,18 +85,24 @@ void raid_gen3_avx2ext(int nd, size_t size, void **vv);
 void raid_gen4_int8(int nd, size_t size, void **vv);
 void raid_gen4_ssse3(int nd, size_t size, void **vv);
 void raid_gen4_ssse3ext(int nd, size_t size, void **vv);
+void raid_gen4_avx2ext(int nd, size_t size, void **vv);
 void raid_gen5_int8(int nd, size_t size, void **vv);
 void raid_gen5_ssse3(int nd, size_t size, void **vv);
 void raid_gen5_ssse3ext(int nd, size_t size, void **vv);
+void raid_gen5_avx2ext(int nd, size_t size, void **vv);
 void raid_gen6_int8(int nd, size_t size, void **vv);
 void raid_gen6_ssse3(int nd, size_t size, void **vv);
 void raid_gen6_ssse3ext(int nd, size_t size, void **vv);
+void raid_gen6_avx2ext(int nd, size_t size, void **vv);
 void raid_rec1_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 void raid_rec2_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 void raid_recX_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 void raid_rec1_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 void raid_rec2_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 void raid_recX_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
+void raid_rec1_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
+void raid_rec2_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
+void raid_recX_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
 
 /*
  * Internal naming.
diff --git a/raid/module.c b/raid/module.c
index 334f10b2..c5b1b8e1 100644
--- a/raid/module.c
+++ b/raid/module.c
@@ -86,7 +86,16 @@ void raid_init(void)
 #ifdef CONFIG_X86_64
 		raid_gen3_ptr = raid_gen3_avx2ext;
 		raid_genz_ptr = raid_genz_avx2ext;
+		raid_gen_ptr[3] = raid_gen4_avx2ext;
+		raid_gen_ptr[4] = raid_gen5_avx2ext;
+		raid_gen_ptr[5] = raid_gen6_avx2ext;
 #endif
+		raid_rec_ptr[0] = raid_rec1_avx2;
+		raid_rec_ptr[1] = raid_rec2_avx2;
+		raid_rec_ptr[2] = raid_recX_avx2;
+		raid_rec_ptr[3] = raid_recX_avx2;
+		raid_rec_ptr[4] = raid_recX_avx2;
+		raid_rec_ptr[5] = raid_recX_avx2;
 	}
 #endif
 
diff --git a/raid/tag.c b/raid/tag.c
index 250dbec4..1141691c 100644
--- a/raid/tag.c
+++ b/raid/tag.c
@@ -45,6 +45,9 @@ static struct raid_func {
 	{ "ssse3", raid_recX_ssse3 },
 	{ "avx2", raid_gen1_avx2 },
 	{ "avx2", raid_gen2_avx2 },
+	{ "avx2", raid_rec1_avx2 },
+	{ "avx2", raid_rec2_avx2 },
+	{ "avx2", raid_recX_avx2 },
 #endif
 
 #ifdef CONFIG_X86_64
@@ -56,6 +59,9 @@ static struct raid_func {
 	{ "ssse3e", raid_gen6_ssse3ext },
 	{ "avx2e", raid_gen3_avx2ext },
 	{ "avx2e", raid_genz_avx2ext },
+	{ "avx2e", raid_gen4_avx2ext },
+	{ "avx2e", raid_gen5_avx2ext },
+	{ "avx2e", raid_gen6_avx2ext },
 #endif
 	{ 0, 0 }
 };
diff --git a/raid/x86.c b/raid/x86.c
index 2adcb7a2..58ee3c1b 100644
--- a/raid/x86.c
+++ b/raid/x86.c
@@ -87,6 +87,8 @@ void raid_gen1_avx2(int nd, size_t size, void **vv)
 		asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[i+32]));
 	}
 
+	asm volatile("vzeroupper" : : : "memory");
+
 	raid_asm_end();
 }
 #endif
@@ -210,6 +212,8 @@ void raid_gen2_avx2(int nd, size_t size, void **vv)
 		asm volatile("vmovntdq %%ymm3,%0" : "=m" (q[i+32]));
 	}
 
+	asm volatile("vzeroupper" : : : "memory");
+
 	raid_asm_end();
 }
 #endif
@@ -661,6 +665,8 @@ void raid_gen3_avx2ext(int nd, size_t size, void **vv)
 		asm volatile("vmovntdq %%ymm10,%0" : "=m" (r[i+32]));
 	}
 
+	asm volatile("vzeroupper" : : : "memory");
+
 	raid_asm_end();
 }
 #endif
@@ -954,6 +960,169 @@ void raid_gen4_ssse3ext(int nd, size_t size, void **vv)
 }
 #endif
 
+#ifdef CONFIG_X86_64
+/*
+ * GEN4 (quad parity with Cauchy matrix) AVX2 implementation
+ *
+ * Note that it uses 16 registers, meaning that x64 is required.
+ */
+void raid_gen4_avx2ext(int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	uint8_t *p;
+	uint8_t *q;
+	uint8_t *r;
+	uint8_t *s;
+	int d, l;
+	size_t i;
+
+	l = nd - 1;
+	p = v[nd];
+	q = v[nd+1];
+	r = v[nd+2];
+	s = v[nd+3];
+
+	/* special case with only one data disk */
+	if (l == 0) {
+		for (i = 0; i < 4; ++i)
+			memcpy(v[1+i], v[0], size);
+		return;
+	}
+
+	raid_asm_begin();
+
+	/* generic case with at least two data disks */
+	for (i = 0; i < size; i += 64) {
+		/* last disk without the by two multiplication */
+		asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfconst16.low4[0]));
+		asm volatile("vmovdqa %0,%%ymm4" : : "m" (v[l][i]));
+		asm volatile("vmovdqa %0,%%ymm12" : : "m" (v[l][i+32]));
+
+		asm volatile("vmovdqa %ymm4,%ymm0");
+		asm volatile("vmovdqa %ymm4,%ymm1");
+		asm volatile("vmovdqa %ymm12,%ymm8");
+		asm volatile("vmovdqa %ymm12,%ymm9");
+
+		asm volatile("vpsrlw  $4,%ymm4,%ymm5");
+		asm volatile("vpsrlw  $4,%ymm12,%ymm13");
+		asm volatile("vpand   %ymm15,%ymm4,%ymm4");
+		asm volatile("vpand   %ymm15,%ymm12,%ymm12");
+		asm volatile("vpand   %ymm15,%ymm5,%ymm5");
+		asm volatile("vpand   %ymm15,%ymm13,%ymm13");
+
+		asm volatile("vbroadcasti128 %0,%%ymm10" : : "m" (gfgenpshufb[l][0][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfgenpshufb[l][0][1][0]));
+		asm volatile("vpshufb %ymm4,%ymm10,%ymm2");
+		asm volatile("vpshufb %ymm5,%ymm15,%ymm7");
+		asm volatile("vpshufb %ymm12,%ymm10,%ymm10");
+		asm volatile("vpshufb %ymm13,%ymm15,%ymm15");
+		asm volatile("vpxor   %ymm7,%ymm2,%ymm2");
+		asm volatile("vpxor   %ymm15,%ymm10,%ymm10");
+
+		asm volatile("vbroadcasti128 %0,%%ymm11" : : "m" (gfgenpshufb[l][1][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfgenpshufb[l][1][1][0]));
+		asm volatile("vpshufb %ymm4,%ymm11,%ymm3");
+		asm volatile("vpshufb %ymm5,%ymm15,%ymm7");
+		asm volatile("vpshufb %ymm12,%ymm11,%ymm11");
+		asm volatile("vpshufb %ymm13,%ymm15,%ymm15");
+		asm volatile("vpxor   %ymm7,%ymm3,%ymm3");
+		asm volatile("vpxor   %ymm15,%ymm11,%ymm11");
+
+		/* intermediate disks */
+		for (d = l-1; d > 0; --d) {
+			asm volatile("vbroadcasti128 %0,%%ymm7" : : "m" (gfconst16.poly[0]));
+			asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfconst16.low4[0]));
+			asm volatile("vmovdqa %0,%%ymm4" : : "m" (v[d][i]));
+			asm volatile("vmovdqa %0,%%ymm12" : : "m" (v[d][i+32]));
+
+			asm volatile("vpxor %ymm5,%ymm5,%ymm5");
+			asm volatile("vpxor %ymm13,%ymm13,%ymm13");
+			asm volatile("vpcmpgtb %ymm1,%ymm5,%ymm5");
+			asm volatile("vpcmpgtb %ymm9,%ymm13,%ymm13");
+			asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+			asm volatile("vpaddb %ymm9,%ymm9,%ymm9");
+			asm volatile("vpand %ymm7,%ymm5,%ymm5");
+			asm volatile("vpand %ymm7,%ymm13,%ymm13");
+			asm volatile("vpxor %ymm5,%ymm1,%ymm1");
+			asm volatile("vpxor %ymm13,%ymm9,%ymm9");
+
+			asm volatile("vpxor %ymm4,%ymm0,%ymm0");
+			asm volatile("vpxor %ymm4,%ymm1,%ymm1");
+			asm volatile("vpxor %ymm12,%ymm8,%ymm8");
+			asm volatile("vpxor %ymm12,%ymm9,%ymm9");
+
+			asm volatile("vpsrlw  $4,%ymm4,%ymm5");
+			asm volatile("vpsrlw  $4,%ymm12,%ymm13");
+			asm volatile("vpand   %ymm15,%ymm4,%ymm4");
+			asm volatile("vpand   %ymm15,%ymm12,%ymm12");
+			asm volatile("vpand   %ymm15,%ymm5,%ymm5");
+			asm volatile("vpand   %ymm15,%ymm13,%ymm13");
+
+			asm volatile("vbroadcasti128 %0,%%ymm14" : : "m" (gfgenpshufb[d][0][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfgenpshufb[d][0][1][0]));
+			asm volatile("vpshufb %ymm4,%ymm14,%ymm6");
+			asm volatile("vpshufb %ymm5,%ymm15,%ymm7");
+			asm volatile("vpshufb %ymm12,%ymm14,%ymm14");
+			asm volatile("vpshufb %ymm13,%ymm15,%ymm15");
+			asm volatile("vpxor   %ymm6,%ymm2,%ymm2");
+			asm volatile("vpxor   %ymm14,%ymm10,%ymm10");
+			asm volatile("vpxor   %ymm7,%ymm2,%ymm2");
+			asm volatile("vpxor   %ymm15,%ymm10,%ymm10");
+
+			asm volatile("vbroadcasti128 %0,%%ymm14" : : "m" (gfgenpshufb[d][1][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfgenpshufb[d][1][1][0]));
+			asm volatile("vpshufb %ymm4,%ymm14,%ymm6");
+			asm volatile("vpshufb %ymm5,%ymm15,%ymm7");
+			asm volatile("vpshufb %ymm12,%ymm14,%ymm14");
+			asm volatile("vpshufb %ymm13,%ymm15,%ymm15");
+			asm volatile("vpxor   %ymm6,%ymm3,%ymm3");
+			asm volatile("vpxor   %ymm14,%ymm11,%ymm11");
+			asm volatile("vpxor   %ymm7,%ymm3,%ymm3");
+			asm volatile("vpxor   %ymm15,%ymm11,%ymm11");
+		}
+
+		/* first disk with all coefficients at 1 */
+		asm volatile("vbroadcasti128 %0,%%ymm7" : : "m" (gfconst16.poly[0]));
+		asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfconst16.low4[0]));
+		asm volatile("vmovdqa %0,%%ymm4" : : "m" (v[0][i]));
+		asm volatile("vmovdqa %0,%%ymm12" : : "m" (v[0][i+32]));
+
+		asm volatile("vpxor %ymm5,%ymm5,%ymm5");
+		asm volatile("vpxor %ymm13,%ymm13,%ymm13");
+		asm volatile("vpcmpgtb %ymm1,%ymm5,%ymm5");
+		asm volatile("vpcmpgtb %ymm9,%ymm13,%ymm13");
+		asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+		asm volatile("vpaddb %ymm9,%ymm9,%ymm9");
+		asm volatile("vpand %ymm7,%ymm5,%ymm5");
+		asm volatile("vpand %ymm7,%ymm13,%ymm13");
+		asm volatile("vpxor %ymm5,%ymm1,%ymm1");
+		asm volatile("vpxor %ymm13,%ymm9,%ymm9");
+
+		asm volatile("vpxor %ymm4,%ymm0,%ymm0");
+		asm volatile("vpxor %ymm4,%ymm1,%ymm1");
+		asm volatile("vpxor %ymm4,%ymm2,%ymm2");
+		asm volatile("vpxor %ymm4,%ymm3,%ymm3");
+		asm volatile("vpxor %ymm12,%ymm8,%ymm8");
+		asm volatile("vpxor %ymm12,%ymm9,%ymm9");
+		asm volatile("vpxor %ymm12,%ymm10,%ymm10");
+		asm volatile("vpxor %ymm12,%ymm11,%ymm11");
+
+		asm volatile("vmovntdq %%ymm0,%0" : "=m" (p[i]));
+		asm volatile("vmovntdq %%ymm8,%0" : "=m" (p[i+32]));
+		asm volatile("vmovntdq %%ymm1,%0" : "=m" (q[i]));
+		asm volatile("vmovntdq %%ymm9,%0" : "=m" (q[i+32]));
+		asm volatile("vmovntdq %%ymm2,%0" : "=m" (r[i]));
+		asm volatile("vmovntdq %%ymm10,%0" : "=m" (r[i+32]));
+		asm volatile("vmovntdq %%ymm3,%0" : "=m" (s[i]));
+		asm volatile("vmovntdq %%ymm11,%0" : "=m" (s[i+32]));
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
 #ifdef CONFIG_X86
 /*
  * GEN5 (penta parity with Cauchy matrix) SSSE3 implementation
@@ -963,7 +1132,6 @@ void raid_gen4_ssse3ext(int nd, size_t size, void **vv)
 __attribute__((force_align_arg_pointer))
 #endif
 void raid_gen5_ssse3(int nd, size_t size, void **vv)
-/* ensures that stack is aligned at 16 bytes because we allocate SSE registers in it */
 {
 	uint8_t **v = (uint8_t **)vv;
 	uint8_t *p;
@@ -1228,6 +1396,138 @@ void raid_gen5_ssse3ext(int nd, size_t size, void **vv)
 }
 #endif
 
+#ifdef CONFIG_X86_64
+/*
+ * GEN5 (penta parity with Cauchy matrix) AVX2 implementation
+ *
+ * Note that it uses 16 registers, meaning that x64 is required.
+ */
+void raid_gen5_avx2ext(int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	uint8_t *p;
+	uint8_t *q;
+	uint8_t *r;
+	uint8_t *s;
+	uint8_t *t;
+	int d, l;
+	size_t i;
+
+	l = nd - 1;
+	p = v[nd];
+	q = v[nd+1];
+	r = v[nd+2];
+	s = v[nd+3];
+	t = v[nd+4];
+
+	/* special case with only one data disk */
+	if (l == 0) {
+		for (i = 0; i < 5; ++i)
+			memcpy(v[1+i], v[0], size);
+		return;
+	}
+
+	raid_asm_begin();
+
+	/* generic case with at least two data disks */
+	asm volatile("vpxor %ymm8,%ymm8,%ymm8");
+	asm volatile("vbroadcasti128 %0,%%ymm14" : : "m" (gfconst16.poly[0]));
+	asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfconst16.low4[0]));
+
+	for (i = 0; i < size; i += 32) {
+		/* last disk without the by two multiplication */
+		asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[l][i]));
+
+		asm volatile("vmovdqa %ymm10,%ymm0");
+		asm volatile("vmovdqa %ymm10,%ymm1");
+
+		asm volatile("vpsrlw  $4,%ymm10,%ymm11");
+		asm volatile("vpand   %ymm15,%ymm10,%ymm10");
+		asm volatile("vpand   %ymm15,%ymm11,%ymm11");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfgenpshufb[l][0][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][0][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm2,%ymm2");
+
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfgenpshufb[l][1][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][1][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm3,%ymm3");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm3,%ymm3");
+
+		asm volatile("vbroadcasti128 %0,%%ymm4" : : "m" (gfgenpshufb[l][2][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][2][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm4,%ymm4");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm4,%ymm4");
+
+		/* intermediate disks */
+		for (d = l-1; d > 0; --d) {
+			asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[d][i]));
+
+			asm volatile("vpcmpgtb %ymm1,%ymm8,%ymm11");
+			asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+			asm volatile("vpand %ymm14,%ymm11,%ymm11");
+			asm volatile("vpxor %ymm11,%ymm1,%ymm1");
+
+			asm volatile("vpxor %ymm10,%ymm0,%ymm0");
+			asm volatile("vpxor %ymm10,%ymm1,%ymm1");
+
+			asm volatile("vpsrlw  $4,%ymm10,%ymm11");
+			asm volatile("vpand   %ymm15,%ymm10,%ymm10");
+			asm volatile("vpand   %ymm15,%ymm11,%ymm11");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][0][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][0][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm2,%ymm2");
+			asm volatile("vpxor   %ymm13,%ymm2,%ymm2");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][1][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][1][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm3,%ymm3");
+			asm volatile("vpxor   %ymm13,%ymm3,%ymm3");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][2][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][2][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm4,%ymm4");
+			asm volatile("vpxor   %ymm13,%ymm4,%ymm4");
+		}
+
+		/* first disk with all coefficients at 1 */
+		asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[0][i]));
+
+		asm volatile("vpcmpgtb %ymm1,%ymm8,%ymm11");
+		asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+		asm volatile("vpand %ymm14,%ymm11,%ymm11");
+		asm volatile("vpxor %ymm11,%ymm1,%ymm1");
+
+		asm volatile("vpxor %ymm10,%ymm0,%ymm0");
+		asm volatile("vpxor %ymm10,%ymm1,%ymm1");
+		asm volatile("vpxor %ymm10,%ymm2,%ymm2");
+		asm volatile("vpxor %ymm10,%ymm3,%ymm3");
+		asm volatile("vpxor %ymm10,%ymm4,%ymm4");
+
+		asm volatile("vmovntdq %%ymm0,%0" : "=m" (p[i]));
+		asm volatile("vmovntdq %%ymm1,%0" : "=m" (q[i]));
+		asm volatile("vmovntdq %%ymm2,%0" : "=m" (r[i]));
+		asm volatile("vmovntdq %%ymm3,%0" : "=m" (s[i]));
+		asm volatile("vmovntdq %%ymm4,%0" : "=m" (t[i]));
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
 #ifdef CONFIG_X86
 /*
  * GEN6 (hexa parity with Cauchy matrix) SSSE3 implementation
@@ -1540,6 +1840,155 @@ void raid_gen6_ssse3ext(int nd, size_t size, void **vv)
 }
 #endif
 
+#ifdef CONFIG_X86_64
+/*
+ * GEN6 (hexa parity with Cauchy matrix) AVX2 implementation
+ *
+ * Note that it uses 16 registers, meaning that x64 is required.
+ */
+void raid_gen6_avx2ext(int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	uint8_t *p;
+	uint8_t *q;
+	uint8_t *r;
+	uint8_t *s;
+	uint8_t *t;
+	uint8_t *u;
+	int d, l;
+	size_t i;
+
+	l = nd - 1;
+	p = v[nd];
+	q = v[nd+1];
+	r = v[nd+2];
+	s = v[nd+3];
+	t = v[nd+4];
+	u = v[nd+5];
+
+	/* special case with only one data disk */
+	if (l == 0) {
+		for (i = 0; i < 6; ++i)
+			memcpy(v[1+i], v[0], size);
+		return;
+	}
+
+	raid_asm_begin();
+
+	/* generic case with at least two data disks */
+	asm volatile("vpxor %ymm8,%ymm8,%ymm8");
+	asm volatile("vbroadcasti128 %0,%%ymm14" : : "m" (gfconst16.poly[0]));
+	asm volatile("vbroadcasti128 %0,%%ymm15" : : "m" (gfconst16.low4[0]));
+
+	for (i = 0; i < size; i += 32) {
+		/* last disk without the by two multiplication */
+		asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[l][i]));
+
+		asm volatile("vmovdqa %ymm10,%ymm0");
+		asm volatile("vmovdqa %ymm10,%ymm1");
+
+		asm volatile("vpsrlw  $4,%ymm10,%ymm11");
+		asm volatile("vpand   %ymm15,%ymm10,%ymm10");
+		asm volatile("vpand   %ymm15,%ymm11,%ymm11");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfgenpshufb[l][0][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][0][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm2,%ymm2");
+
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfgenpshufb[l][1][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][1][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm3,%ymm3");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm3,%ymm3");
+
+		asm volatile("vbroadcasti128 %0,%%ymm4" : : "m" (gfgenpshufb[l][2][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][2][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm4,%ymm4");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm4,%ymm4");
+
+		asm volatile("vbroadcasti128 %0,%%ymm5" : : "m" (gfgenpshufb[l][3][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[l][3][1][0]));
+		asm volatile("vpshufb %ymm10,%ymm5,%ymm5");
+		asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+		asm volatile("vpxor   %ymm13,%ymm5,%ymm5");
+
+		/* intermediate disks */
+		for (d = l-1; d > 0; --d) {
+			asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[d][i]));
+
+			asm volatile("vpcmpgtb %ymm1,%ymm8,%ymm11");
+			asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+			asm volatile("vpand %ymm14,%ymm11,%ymm11");
+			asm volatile("vpxor %ymm11,%ymm1,%ymm1");
+
+			asm volatile("vpxor %ymm10,%ymm0,%ymm0");
+			asm volatile("vpxor %ymm10,%ymm1,%ymm1");
+
+			asm volatile("vpsrlw  $4,%ymm10,%ymm11");
+			asm volatile("vpand   %ymm15,%ymm10,%ymm10");
+			asm volatile("vpand   %ymm15,%ymm11,%ymm11");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][0][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][0][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm2,%ymm2");
+			asm volatile("vpxor   %ymm13,%ymm2,%ymm2");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][1][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][1][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm3,%ymm3");
+			asm volatile("vpxor   %ymm13,%ymm3,%ymm3");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][2][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][2][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm4,%ymm4");
+			asm volatile("vpxor   %ymm13,%ymm4,%ymm4");
+
+			asm volatile("vbroadcasti128 %0,%%ymm12" : : "m" (gfgenpshufb[d][3][0][0]));
+			asm volatile("vbroadcasti128 %0,%%ymm13" : : "m" (gfgenpshufb[d][3][1][0]));
+			asm volatile("vpshufb %ymm10,%ymm12,%ymm12");
+			asm volatile("vpshufb %ymm11,%ymm13,%ymm13");
+			asm volatile("vpxor   %ymm12,%ymm5,%ymm5");
+			asm volatile("vpxor   %ymm13,%ymm5,%ymm5");
+		}
+
+		/* first disk with all coefficients at 1 */
+		asm volatile("vmovdqa %0,%%ymm10" : : "m" (v[0][i]));
+
+		asm volatile("vpcmpgtb %ymm1,%ymm8,%ymm11");
+		asm volatile("vpaddb %ymm1,%ymm1,%ymm1");
+		asm volatile("vpand %ymm14,%ymm11,%ymm11");
+		asm volatile("vpxor %ymm11,%ymm1,%ymm1");
+
+		asm volatile("vpxor %ymm10,%ymm0,%ymm0");
+		asm volatile("vpxor %ymm10,%ymm1,%ymm1");
+		asm volatile("vpxor %ymm10,%ymm2,%ymm2");
+		asm volatile("vpxor %ymm10,%ymm3,%ymm3");
+		asm volatile("vpxor %ymm10,%ymm4,%ymm4");
+		asm volatile("vpxor %ymm10,%ymm5,%ymm5");
+
+		asm volatile("vmovntdq %%ymm0,%0" : "=m" (p[i]));
+		asm volatile("vmovntdq %%ymm1,%0" : "=m" (q[i]));
+		asm volatile("vmovntdq %%ymm2,%0" : "=m" (r[i]));
+		asm volatile("vmovntdq %%ymm3,%0" : "=m" (s[i]));
+		asm volatile("vmovntdq %%ymm4,%0" : "=m" (t[i]));
+		asm volatile("vmovntdq %%ymm5,%0" : "=m" (u[i]));
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
 #ifdef CONFIG_X86
 /*
  * RAID recovering for one disk SSSE3 implementation
@@ -1781,3 +2230,239 @@ void raid_recX_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv)
 }
 #endif
 
+
+#ifdef CONFIG_X86
+/*
+ * RAID recovering for one disk AVX2 implementation
+ */
+void raid_rec1_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	uint8_t *p;
+	uint8_t *pa;
+	uint8_t G;
+	uint8_t V;
+	size_t i;
+
+	(void)nr; /* unused, it's always 1 */
+
+	/* if it's RAID5 uses the faster function */
+	if (ip[0] == 0) {
+		raid_rec1of1(id, nd, size, vv);
+		return;
+	}
+
+	/* setup the coefficients matrix */
+	G = A(ip[0], id[0]);
+
+	/* invert it to solve the system of linear equations */
+	V = inv(G);
+
+	/* compute delta parity */
+	raid_delta_gen(1, id, ip, nd, size, vv);
+
+	p = v[nd+ip[0]];
+	pa = v[id[0]];
+
+	raid_asm_begin();
+
+	asm volatile("vbroadcasti128 %0,%%ymm7" : : "m" (gfconst16.low4[0]));
+	asm volatile("vbroadcasti128 %0,%%ymm4" : : "m" (gfmulpshufb[V][0][0]));
+	asm volatile("vbroadcasti128 %0,%%ymm5" : : "m" (gfmulpshufb[V][1][0]));
+
+	for (i = 0; i < size; i += 32) {
+		asm volatile("vmovdqa %0,%%ymm0" : : "m" (p[i]));
+		asm volatile("vmovdqa %0,%%ymm1" : : "m" (pa[i]));
+		asm volatile("vpxor   %ymm1,%ymm0,%ymm0");
+		asm volatile("vpsrlw  $4,%ymm0,%ymm1");
+		asm volatile("vpand   %ymm7,%ymm0,%ymm0");
+		asm volatile("vpand   %ymm7,%ymm1,%ymm1");
+		asm volatile("vpshufb %ymm0,%ymm4,%ymm2");
+		asm volatile("vpshufb %ymm1,%ymm5,%ymm3");
+		asm volatile("vpxor   %ymm3,%ymm2,%ymm2");
+		asm volatile("vmovdqa %%ymm2,%0" : "=m" (pa[i]));
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
+#ifdef CONFIG_X86
+/*
+ * RAID recovering for two disks AVX2 implementation
+ */
+void raid_rec2_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	const int N = 2;
+	uint8_t *p[N];
+	uint8_t *pa[N];
+	uint8_t G[N*N];
+	uint8_t V[N*N];
+	size_t i;
+	int j, k;
+
+	(void)nr; /* unused, it's always 2 */
+
+	/* setup the coefficients matrix */
+	for (j = 0; j < N; ++j)
+		for (k = 0; k < N; ++k)
+			G[j*N+k] = A(ip[j], id[k]);
+
+	/* invert it to solve the system of linear equations */
+	raid_invert(G, V, N);
+
+	/* compute delta parity */
+	raid_delta_gen(N, id, ip, nd, size, vv);
+
+	for (j = 0; j < N; ++j) {
+		p[j] = v[nd+ip[j]];
+		pa[j] = v[id[j]];
+	}
+
+	raid_asm_begin();
+
+	asm volatile("vbroadcasti128 %0,%%ymm7" : : "m" (gfconst16.low4[0]));
+
+	for (i = 0; i < size; i += 32) {
+		asm volatile("vmovdqa %0,%%ymm0" : : "m" (p[0][i]));
+		asm volatile("vmovdqa %0,%%ymm2" : : "m" (pa[0][i]));
+		asm volatile("vmovdqa %0,%%ymm1" : : "m" (p[1][i]));
+		asm volatile("vmovdqa %0,%%ymm3" : : "m" (pa[1][i]));
+		asm volatile("vpxor   %ymm2,%ymm0,%ymm0");
+		asm volatile("vpxor   %ymm3,%ymm1,%ymm1");
+
+		asm volatile("vpxor %ymm6,%ymm6,%ymm6");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfmulpshufb[V[0]][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfmulpshufb[V[0]][1][0]));
+		asm volatile("vpsrlw  $4,%ymm0,%ymm5");
+		asm volatile("vpand   %ymm7,%ymm0,%ymm4");
+		asm volatile("vpand   %ymm7,%ymm5,%ymm5");
+		asm volatile("vpshufb %ymm4,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm5,%ymm3,%ymm3");
+		asm volatile("vpxor   %ymm2,%ymm6,%ymm6");
+		asm volatile("vpxor   %ymm3,%ymm6,%ymm6");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfmulpshufb[V[1]][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfmulpshufb[V[1]][1][0]));
+		asm volatile("vpsrlw  $4,%ymm1,%ymm5");
+		asm volatile("vpand   %ymm7,%ymm1,%ymm4");
+		asm volatile("vpand   %ymm7,%ymm5,%ymm5");
+		asm volatile("vpshufb %ymm4,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm5,%ymm3,%ymm3");
+		asm volatile("vpxor   %ymm2,%ymm6,%ymm6");
+		asm volatile("vpxor   %ymm3,%ymm6,%ymm6");
+
+		asm volatile("vmovdqa %%ymm6,%0" : "=m" (pa[0][i]));
+
+		asm volatile("vpxor %ymm6,%ymm6,%ymm6");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfmulpshufb[V[2]][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfmulpshufb[V[2]][1][0]));
+		asm volatile("vpsrlw  $4,%ymm0,%ymm5");
+		asm volatile("vpand   %ymm7,%ymm0,%ymm4");
+		asm volatile("vpand   %ymm7,%ymm5,%ymm5");
+		asm volatile("vpshufb %ymm4,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm5,%ymm3,%ymm3");
+		asm volatile("vpxor   %ymm2,%ymm6,%ymm6");
+		asm volatile("vpxor   %ymm3,%ymm6,%ymm6");
+
+		asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfmulpshufb[V[3]][0][0]));
+		asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfmulpshufb[V[3]][1][0]));
+		asm volatile("vpsrlw  $4,%ymm1,%ymm5");
+		asm volatile("vpand   %ymm7,%ymm1,%ymm4");
+		asm volatile("vpand   %ymm7,%ymm5,%ymm5");
+		asm volatile("vpshufb %ymm4,%ymm2,%ymm2");
+		asm volatile("vpshufb %ymm5,%ymm3,%ymm3");
+		asm volatile("vpxor   %ymm2,%ymm6,%ymm6");
+		asm volatile("vpxor   %ymm3,%ymm6,%ymm6");
+
+		asm volatile("vmovdqa %%ymm6,%0" : "=m" (pa[1][i]));
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
+#ifdef CONFIG_X86
+/*
+ * RAID recovering AVX2 implementation
+ */
+void raid_recX_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv)
+{
+	uint8_t **v = (uint8_t **)vv;
+	int N = nr;
+	uint8_t *p[RAID_PARITY_MAX];
+	uint8_t *pa[RAID_PARITY_MAX];
+	uint8_t G[RAID_PARITY_MAX*RAID_PARITY_MAX];
+	uint8_t V[RAID_PARITY_MAX*RAID_PARITY_MAX];
+	size_t i;
+	int j, k;
+
+	/* setup the coefficients matrix */
+	for (j = 0; j < N; ++j)
+		for (k = 0; k < N; ++k)
+			G[j*N+k] = A(ip[j], id[k]);
+
+	/* invert it to solve the system of linear equations */
+	raid_invert(G, V, N);
+
+	/* compute delta parity */
+	raid_delta_gen(N, id, ip, nd, size, vv);
+
+	for (j = 0; j < N; ++j) {
+		p[j] = v[nd+ip[j]];
+		pa[j] = v[id[j]];
+	}
+
+	raid_asm_begin();
+
+	asm volatile("vbroadcasti128 %0,%%ymm7" : : "m" (gfconst16.low4[0]));
+
+	for (i = 0; i < size; i += 32) {
+		uint8_t PD[RAID_PARITY_MAX][32] __aligned(32);
+
+		/* delta */
+		for (j = 0; j < N; ++j) {
+			asm volatile("vmovdqa %0,%%ymm0" : : "m" (p[j][i]));
+			asm volatile("vmovdqa %0,%%ymm1" : : "m" (pa[j][i]));
+			asm volatile("vpxor   %ymm1,%ymm0,%ymm0");
+			asm volatile("vmovdqa %%ymm0,%0" : "=m" (PD[j][0]));
+		}
+
+		/* reconstruct */
+		for (j = 0; j < N; ++j) {
+			asm volatile("vpxor %ymm0,%ymm0,%ymm0");
+			asm volatile("vpxor %ymm1,%ymm1,%ymm1");
+
+			for (k = 0; k < N; ++k) {
+				uint8_t m = V[j*N+k];
+
+				asm volatile("vbroadcasti128 %0,%%ymm2" : : "m" (gfmulpshufb[m][0][0]));
+				asm volatile("vbroadcasti128 %0,%%ymm3" : : "m" (gfmulpshufb[m][1][0]));
+				asm volatile("vmovdqa %0,%%ymm4" : : "m" (PD[k][0]));
+				asm volatile("vpsrlw  $4,%ymm4,%ymm5");
+				asm volatile("vpand   %ymm7,%ymm4,%ymm4");
+				asm volatile("vpand   %ymm7,%ymm5,%ymm5");
+				asm volatile("vpshufb %ymm4,%ymm2,%ymm2");
+				asm volatile("vpshufb %ymm5,%ymm3,%ymm3");
+				asm volatile("vpxor   %ymm2,%ymm0,%ymm0");
+				asm volatile("vpxor   %ymm3,%ymm1,%ymm1");
+			}
+
+			asm volatile("vpxor %ymm1,%ymm0,%ymm0");
+			asm volatile("vmovdqa %%ymm0,%0" : "=m" (pa[j][i]));
+		}
+	}
+
+	asm volatile("vzeroupper" : : : "memory");
+
+	raid_asm_end();
+}
+#endif
+
diff --git a/raid/x86z.c b/raid/x86z.c
index 875ac5b8..45f168cc 100644
--- a/raid/x86z.c
+++ b/raid/x86z.c
@@ -248,6 +248,8 @@ void raid_genz_avx2ext(int nd, size_t size, void **vv)
 		asm volatile("vmovntdq %%ymm10,%0" : "=m" (r[i+32]));
 	}
 
+	asm volatile("vzeroupper" : : : "memory");
+
 	raid_asm_end();
 }
 #endif