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https://github.com/amadvance/snapraid.git
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Preliminary support for ADVX512
This commit is contained in:
Andrea Mazzoleni
parent
cf515b82b2
commit
d0fb6d2ac3
7 changed files with 157 additions and 4 deletions
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@ -382,13 +382,14 @@ else
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if !HAVE_MEMORY_CHECKER
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if HAVE_EMULATOR
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$(MSG) Speed
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# Run the self test in AVX2
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$(TESTENV_AVX2) $(SNAPRAID) --test-skip-device -c $(CONF) status
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# Run the self test in AVX512
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$(TESTENV_AVX512) $(SNAPRAID) --test-skip-device -c $(CONF) status
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# Run the speed test in different architectures
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$(TESTENV_SSE2) $(SNAPRAID) --test-skip-device -T
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$(TESTENV_SSSE3) $(SNAPRAID) --test-skip-device -T
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$(TESTENV_SSE42) $(SNAPRAID) --test-skip-device -T
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$(TESTENV_AVX2) $(SNAPRAID) --test-skip-device -T
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$(TESTENV_AVX512) $(SNAPRAID) --test-skip-device -T
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else
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# Run the self test natively
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$(TESTENV) $(SNAPRAID) --test-skip-device -c $(CONF) status
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21
configure.ac
21
configure.ac
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@ -242,6 +242,22 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
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[AC_DEFINE([HAVE_AVX2], [1], [Define to 1 if avx2 is supported by the assembler.]) asmavx2=yes])
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AC_MSG_RESULT([$asmavx2])
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dnl Checks for AS supporting the AVX512BW instructions.
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AC_MSG_CHECKING([for avx512bw])
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asmavx512bw=no
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AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
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#if defined(__i386__) || defined(__x86_64__)
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void f(void* ptr)
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{
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asm volatile("vpshufb %0, %%zmm0, %%zmm1" : : "m" (ptr));
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}
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#else
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#error not x86
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#endif
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]])],
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[AC_DEFINE([HAVE_AVX512BW], [1], [Define to 1 if avx512bw is supported by the assembler.]) asmavx512bw=yes])
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AC_MSG_RESULT([$asmavx512bw])
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dnl AS_IF(HAVE_ASSEMBLY) closed here
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)
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@ -353,12 +369,14 @@ dnl p4p -> Pentium4 Prescott with SSE2
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dnl mrm -> Merom with SSSE3
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dnl nhm -> Nehalem with SSE4.2
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dnl hsw -> Haswell with AVX2
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dnl knl -> Knights Landing with AVX512
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dnl knl -> Knights Landing with AVX512F
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dnl skx -> Skylake Xeon with AVX512BW
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[
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TESTENV_SSE2="$SDE -chip-check-exe-only -p4p --"
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TESTENV_SSSE3="$SDE -chip-check-exe-only -mrm --"
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TESTENV_SSE42="$SDE -nhm --"
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TESTENV_AVX2="$SDE -hsw --"
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TESTENV_AVX512="$SDE -skx --"
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EMULATOR=1
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# Target CPU compatible with P4 Prescott
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CFLAGS="$CFLAGS -march=athlon64"
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@ -402,6 +420,7 @@ AC_ARG_VAR([TESTENV_SSE2], [Test environment for SSE2])
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AC_ARG_VAR([TESTENV_SSSE3], [Test environment for SSSE3])
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AC_ARG_VAR([TESTENV_SSE42], [Test environment for SSE42])
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AC_ARG_VAR([TESTENV_AVX2], [Test environment for AVX2])
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AC_ARG_VAR([TESTENV_AVX512], [Test environment for AVX512])
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AC_CONFIG_FILES([Makefile])
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AC_CONFIG_FILES([pkg/snapraid.info pkg/control pkg/snapraid.spec pkg/.PKGINFO pkg/PKGBUILD pkg/.SRCINFO])
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@ -43,6 +43,10 @@
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#define CONFIG_AVX2 1
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#endif
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#if HAVE_AVX512BW /* Enables AVX2512BW only if the assembler supports it */
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#define CONFIG_AVX512BW 1
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#endif
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#else /* if HAVE_CONFIG_H is not defined */
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/* Assume that assembly is always supported */
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@ -61,6 +65,7 @@
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#define CONFIG_SSE2 1
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#define CONFIG_SSSE3 1
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#define CONFIG_AVX2 1
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#define CONFIG_AVX512BW 1
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#endif
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#endif
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@ -123,11 +128,13 @@ void raid_gen1_int32(int nd, size_t size, void **vv);
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void raid_gen1_int64(int nd, size_t size, void **vv);
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void raid_gen1_sse2(int nd, size_t size, void **vv);
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void raid_gen1_avx2(int nd, size_t size, void **vv);
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void raid_gen1_avx512bw(int nd, size_t size, void **vv);
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void raid_gen2_int32(int nd, size_t size, void **vv);
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void raid_gen2_int64(int nd, size_t size, void **vv);
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void raid_gen2_sse2(int nd, size_t size, void **vv);
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void raid_gen2_avx2(int nd, size_t size, void **vv);
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void raid_gen2_sse2ext(int nd, size_t size, void **vv);
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void raid_gen2_avx512bw(int nd, size_t size, void **vv);
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void raid_genz_int32(int nd, size_t size, void **vv);
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void raid_genz_int64(int nd, size_t size, void **vv);
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void raid_genz_sse2(int nd, size_t size, void **vv);
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@ -354,6 +354,13 @@ int raid_test_par(int mode, int nd, size_t size)
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f[nf++] = raid_gen2_avx2;
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}
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#endif
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#ifdef CONFIG_AVX512BW
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if (raid_cpu_has_avx512bw()) {
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f[nf++] = raid_gen1_avx512bw;
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f[nf++] = raid_gen2_avx512bw;
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}
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#endif
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#endif /* CONFIG_X86 */
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if (mode == RAID_MODE_CAUCHY) {
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@ -73,10 +73,15 @@ sdecovtest:
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$(SDE) -mrm -- ./selftest
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$(SDE) -nhm -- ./selftest
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$(SDE) -hsw -- ./selftest
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$(SDE) -hsw -- ./speedtest
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$(SDE) -skx -- ./selftest
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$(SDE) -icl -- ./selftest
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$(SDE) -icl -- ./speedtest
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$(MAKE) lcov_capture
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$(MAKE) lcov_html
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sde:
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$(SDE) -icl -- ./speedtest
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lcov_reset:
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lcov --directory . -z
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rm -f lcov.info
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@ -137,6 +137,7 @@ void speed(void)
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printf("%8s", "avx2");
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#ifdef CONFIG_X86_64
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printf("%8s", "avx2e");
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printf("%8s", "avx512");
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#endif
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#endif
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printf("\n");
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@ -191,6 +192,18 @@ void speed(void)
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fflush(stdout);
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}
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#endif
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#ifdef CONFIG_AVX512BW
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if (raid_cpu_has_avx512bw()) {
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printf("%8s", "");
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SPEED_START {
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raid_gen1_avx512bw(nd, size, v);
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} SPEED_STOP
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printf("%8" PRIu64, ds / dt);
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fflush(stdout);
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}
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#endif
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#endif
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printf("\n");
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@ -250,6 +263,18 @@ void speed(void)
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fflush(stdout);
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}
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#endif
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#ifdef CONFIG_AVX512BW
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if (raid_cpu_has_avx512bw()) {
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printf("%8s", "");
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SPEED_START {
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raid_gen2_avx512bw(nd, size, v);
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} SPEED_STOP
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printf("%8" PRIu64, ds / dt);
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fflush(stdout);
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}
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#endif
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#endif
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printf("\n");
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@ -858,6 +883,10 @@ int main(void)
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printf("Including x86 SSSE3 functions\n");
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if (raid_cpu_has_avx2())
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printf("Including x86 AVX2 functions\n");
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if (raid_cpu_has_avx512bw())
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printf("Including x86 AVX512bw functions\n");
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if (raid_cpu_has_avx512gfni())
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printf("Including x86 AVX512gfni functions\n");
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#endif
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#ifdef CONFIG_X86_64
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printf("Including x64 extended SSE register set\n");
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85
raid/x86.c
85
raid/x86.c
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@ -91,6 +91,42 @@ void raid_gen1_avx2(int nd, size_t size, void **vv)
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}
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#endif
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#if defined(CONFIG_X86) && defined(CONFIG_AVX512BW)
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/*
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* GEN1 (RAID5 with xor) AVX512BW implementation
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*
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* Note that in true AVX512F would suffice, but we don't want to add
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* specific support for AVX512F because this would be the only function
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* to benefit from that.
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*
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* Intentionally don't process more than 64 bytes because 64 is the typical
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* cache block, and processing 128 bytes doesn't increase performance, and in
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* some cases it even decreases it.
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*/
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void raid_gen1_avx512bw(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t**)vv;
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uint8_t *p;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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raid_avx_begin();
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for (i = 0; i < size; i += 64) {
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asm volatile ("vmovdqa64 %0,%%zmm0" : : "m" (v[l][i]));
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for (d = l - 1; d >= 0; --d) {
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asm volatile ("vpxorq %0,%%zmm0,%%zmm0" : : "m" (v[d][i]));
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}
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asm volatile ("vmovntdq %%zmm0,%0" : "=m" (p[i]));
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}
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raid_avx_end();
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}
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#endif
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#if defined(CONFIG_X86) && defined(CONFIG_SSE2)
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static const struct gfconst16 {
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uint8_t poly[16];
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@ -214,6 +250,48 @@ void raid_gen2_avx2(int nd, size_t size, void **vv)
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}
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#endif
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#if defined(CONFIG_X86) && defined(CONFIG_AVX512BW)
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/*
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* GEN2 (RAID6 with powers of 2) AVX512BW implementation
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*/
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void raid_gen2_avx512bw(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t**)vv;
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uint8_t *p;
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uint8_t *q;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd + 1];
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raid_avx_begin();
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asm volatile ("vbroadcasti32x4 %0, %%zmm7" : : "m" (gfconst16.poly[0]));
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asm volatile ("vpxorq %zmm6,%zmm6,%zmm6");
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for (i = 0; i < size; i += 64) {
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asm volatile ("vmovdqa64 %0,%%zmm0" : : "m" (v[l][i]));
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asm volatile ("vmovdqa64 %zmm0,%zmm2");
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for (d = l - 1; d >= 0; --d) {
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asm volatile ("vpcmpgtb %zmm2,%zmm6,%k1");
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asm volatile ("vpaddb %zmm2,%zmm2,%zmm2");
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asm volatile ("vmovdqu8 %zmm7,%zmm4{%k1}{z}");
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asm volatile ("vpxorq %zmm4,%zmm2,%zmm2");
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asm volatile ("vmovdqa64 %0,%%zmm4" : : "m" (v[d][i]));
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asm volatile ("vpxorq %zmm4,%zmm0,%zmm0");
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asm volatile ("vpxorq %zmm4,%zmm2,%zmm2");
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}
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asm volatile ("vmovntdq %%zmm0,%0" : "=m" (p[i]));
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asm volatile ("vmovntdq %%zmm2,%0" : "=m" (q[i]));
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}
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raid_avx_end();
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}
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#endif
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#if defined(CONFIG_X86_64) && defined(CONFIG_SSE2)
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/*
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* GEN2 (RAID6 with powers of 2) SSE2 implementation
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@ -2502,5 +2580,12 @@ void raid_register_x86(void)
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raid_rec_register(RAID_ALGO_CAUCHY_PAR6, "avx2", raid_recX_avx2);
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}
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#endif
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#ifdef CONFIG_AVX512BW
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if (raid_cpu_has_avx512bw()) {
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raid_gen_register(RAID_ALGO_CAUCHY_PAR1, "avx512bw", raid_gen1_avx512bw);
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raid_gen_register(RAID_ALGO_CAUCHY_PAR2, "avx512bw", raid_gen2_avx512bw);
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}
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#endif
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}
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#endif
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