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Adds RAID6 mmx/sse2 unroll by 4.
This commit is contained in:
Andrea Mazzoleni
parent
77bd47f2bb
commit
e92035284f
4 changed files with 123 additions and 27 deletions
4
HISTORY
4
HISTORY
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@ -4,7 +4,9 @@ SnapRAID HISTORY
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3.2 2013/6
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==========
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* Better selection of the RAID6 implementation for different CPUs.
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* Adds support for the new Spooky hash. It's faster in 64 bit architectures.
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* Adds the new Spooky hash. It's faster in 64 bit architectures.
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* Adds RAID5/RAID6 mmx and sse2 implementations with unrolling by 4.
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They are a little faster than the previous unroll by 2.
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3.1 2013/5
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==========
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133
raid.c
133
raid.c
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@ -351,38 +351,115 @@ void raid6_sse2r2(unsigned char** buffer, unsigned diskmax, unsigned size)
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p = buffer[z0+1]; /* XOR parity */
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q = buffer[z0+2]; /* RS qarity */
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm4,%xmm4"); /* Zero temp */
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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asm volatile("pxor %xmm7,%xmm7"); /* Zero temp */
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/* We uniformly assume a single prefetch covers at least 32 bytes */
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for(d=0;d<size;d+=32) {
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asm volatile("movdqa %0,%%xmm2" : : "m" (buffer[z0][d])); /* P[0] */
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asm volatile("movdqa %0,%%xmm3" : : "m" (buffer[z0][d+16])); /* P[1] */
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asm volatile("movdqa %xmm2,%xmm4"); /* Q[0] */
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asm volatile("movdqa %xmm3,%xmm6"); /* Q[1] */
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asm volatile("movdqa %0,%%xmm0" : : "m" (buffer[z0][d])); /* P[0] */
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asm volatile("movdqa %0,%%xmm1" : : "m" (buffer[z0][d+16])); /* P[1] */
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asm volatile("movdqa %xmm0,%xmm2"); /* Q[0] */
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asm volatile("movdqa %xmm1,%xmm3"); /* Q[1] */
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for(z=z0-1;z>=0;--z) {
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("pcmpgtb %xmm6,%xmm7");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("paddb %xmm6,%xmm6");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pand %xmm0,%xmm7");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("movdqa %0,%%xmm5" : : "m" (buffer[z][d]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (buffer[z][d+16]));
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asm volatile("pxor %xmm5,%xmm2");
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asm volatile("pxor %xmm7,%xmm3");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("pcmpgtb %xmm2,%xmm4");
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asm volatile("pcmpgtb %xmm3,%xmm5");
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asm volatile("paddb %xmm2,%xmm2");
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asm volatile("paddb %xmm3,%xmm3");
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asm volatile("pand %xmm7,%xmm4");
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asm volatile("pand %xmm7,%xmm5");
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asm volatile("pxor %xmm4,%xmm2");
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asm volatile("pxor %xmm5,%xmm3");
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asm volatile("movdqa %0,%%xmm4" : : "m" (buffer[z][d]));
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asm volatile("movdqa %0,%%xmm5" : : "m" (buffer[z][d+16]));
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asm volatile("pxor %xmm4,%xmm0");
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asm volatile("pxor %xmm5,%xmm1");
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asm volatile("pxor %xmm4,%xmm2");
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asm volatile("pxor %xmm5,%xmm3");
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asm volatile("pxor %xmm4,%xmm4");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm7,%xmm7");
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}
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+16]));
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asm volatile("movntdq %%xmm0,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm1,%0" : "=m" (p[d+16]));
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asm volatile("movntdq %%xmm2,%0" : "=m" (q[d]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (q[d+16]));
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}
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asm volatile("sfence" : : : "memory");
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}
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#endif
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#if defined(__x86_64__)
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/*
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* Unrolled-by-4 SSE2 implementation
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*/
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void raid6_sse2r4(unsigned char** buffer, unsigned diskmax, unsigned size)
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{
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unsigned char* p;
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unsigned char* q;
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int z, z0;
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unsigned d;
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z0 = diskmax - 1; /* Highest data disk */
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p = buffer[z0+1]; /* XOR parity */
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q = buffer[z0+2]; /* RS qarity */
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asm volatile("movdqa %0,%%xmm15" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm8,%xmm8"); /* Zero temp */
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asm volatile("pxor %xmm9,%xmm9"); /* Zero temp */
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asm volatile("pxor %xmm10,%xmm10"); /* Zero temp */
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asm volatile("pxor %xmm11,%xmm11"); /* Zero temp */
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for(d=0;d<size;d+=64) {
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asm volatile("movdqa %0,%%xmm0" : : "m" (buffer[z0][d])); /* P[0] */
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asm volatile("movdqa %0,%%xmm1" : : "m" (buffer[z0][d+16])); /* P[1] */
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asm volatile("movdqa %0,%%xmm2" : : "m" (buffer[z0][d+32])); /* P[2] */
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asm volatile("movdqa %0,%%xmm3" : : "m" (buffer[z0][d+48])); /* P[3] */
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asm volatile("movdqa %xmm0,%xmm4"); /* Q[0] */
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asm volatile("movdqa %xmm1,%xmm5"); /* Q[1] */
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asm volatile("movdqa %xmm2,%xmm6"); /* Q[2] */
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asm volatile("movdqa %xmm3,%xmm7"); /* Q[3] */
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for(z=z0-1;z>=0;--z) {
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asm volatile("pcmpgtb %xmm4,%xmm8");
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asm volatile("pcmpgtb %xmm5,%xmm9");
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asm volatile("pcmpgtb %xmm6,%xmm10");
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asm volatile("pcmpgtb %xmm7,%xmm11");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("paddb %xmm5,%xmm5");
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asm volatile("paddb %xmm6,%xmm6");
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asm volatile("paddb %xmm7,%xmm7");
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asm volatile("pand %xmm15,%xmm8");
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asm volatile("pand %xmm15,%xmm9");
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asm volatile("pand %xmm15,%xmm10");
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asm volatile("pand %xmm15,%xmm11");
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asm volatile("pxor %xmm8,%xmm4");
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asm volatile("pxor %xmm9,%xmm5");
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asm volatile("pxor %xmm10,%xmm6");
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asm volatile("pxor %xmm11,%xmm7");
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asm volatile("movdqa %0,%%xmm8" : : "m" (buffer[z][d]));
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asm volatile("movdqa %0,%%xmm9" : : "m" (buffer[z][d+16]));
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asm volatile("movdqa %0,%%xmm10" : : "m" (buffer[z][d+32]));
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asm volatile("movdqa %0,%%xmm11" : : "m" (buffer[z][d+48]));
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asm volatile("pxor %xmm8,%xmm0");
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asm volatile("pxor %xmm9,%xmm1");
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asm volatile("pxor %xmm10,%xmm2");
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asm volatile("pxor %xmm11,%xmm3");
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asm volatile("pxor %xmm8,%xmm4");
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asm volatile("pxor %xmm9,%xmm5");
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asm volatile("pxor %xmm10,%xmm6");
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asm volatile("pxor %xmm11,%xmm7");
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asm volatile("pxor %xmm8,%xmm8");
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asm volatile("pxor %xmm9,%xmm9");
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asm volatile("pxor %xmm10,%xmm10");
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asm volatile("pxor %xmm11,%xmm11");
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}
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asm volatile("movntdq %%xmm0,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm1,%0" : "=m" (p[d+16]));
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d+32]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+48]));
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asm volatile("movntdq %%xmm4,%0" : "=m" (q[d]));
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+16]));
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asm volatile("movntdq %%xmm5,%0" : "=m" (q[d+16]));
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+32]));
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asm volatile("movntdq %%xmm7,%0" : "=m" (q[d+48]));
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}
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asm volatile("sfence" : : : "memory");
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@ -495,13 +572,17 @@ void raid_init(void)
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raid6_gen = raid6_int32r2;
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#if defined(__i386__) || defined(__x86_64__)
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if (cpu_has_mmx()) {
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raid5_gen = raid5_mmxr2;
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raid5_gen = raid5_mmxr4;
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raid6_gen = raid6_mmxr2;
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}
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if (cpu_has_sse2()) {
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raid5_gen = raid5_sse2r4;
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if (!cpu_has_slowsse2())
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#if defined(__x86_64__)
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raid6_gen = raid6_sse2r4;
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#else
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raid6_gen = raid6_sse2r2;
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#endif
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}
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#endif
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}
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1
raid.h
1
raid.h
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@ -57,6 +57,7 @@ void raid5_sse2r4(unsigned char** dptr, unsigned diskmax, unsigned size);
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void raid6_int32r2(unsigned char** dptr, unsigned diskmax, unsigned size);
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void raid6_mmxr2(unsigned char** dptr, unsigned diskmax, unsigned size);
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void raid6_sse2r2(unsigned char** dptr, unsigned diskmax, unsigned size);
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void raid6_sse2r4(unsigned char** buffer, unsigned diskmax, unsigned size);
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#endif
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12
speed.c
12
speed.c
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@ -130,7 +130,11 @@ void speed(void)
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printf("\n");
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printf("Expected fastest RAID6 is ");
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if (cpu_has_sse2() && !cpu_has_slowsse2())
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#if defined(__x86_64__)
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printf("sse2x4");
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#else
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printf("sse2x2");
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#endif
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else if (cpu_has_mmx())
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printf("mmxx2");
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else
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@ -224,6 +228,14 @@ void speed(void)
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} SPEED_STOP
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printf("RAID6 sse2x2 %"PRIu64" [MB/s]\n", ds / dt);
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#if defined(__x86_64__)
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SPEED_START {
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raid6_sse2r4(buffer, diskmax, block_size);
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} SPEED_STOP
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printf("RAID6 sse2x4 %"PRIu64" [MB/s]\n", ds / dt);
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#endif
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}
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#endif
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