8 commits

Author	SHA1	Message	Date
Andrea Mazzoleni	335f2619fd	Optimize triple parity generation by preloading multiplication tables in vector registers	2026-08-21 12:06:26 +02:00
Andrea Mazzoleni	8c456ee354	Optimize dual parity generation by preloading multiplication tables in vector registers ... Optimize AVX2 and AVX-512 GFNI AES dual parity generation by preloading coefficients in registers	2026-08-21 12:06:26 +02:00
Andrea Mazzoleni	7d434954e8	Precalculate shuffle table pointers outside data loop in Cauchy recX	2026-08-21 12:06:25 +02:00
Andrea Mazzoleni	7f6ef3b4cd	Eliminate stack buffers, pre-split delta nibbles and and inner loop in recX	2026-08-21 12:06:25 +02:00
Andrea Mazzoleni	7e2a8eab7d	Keep multiplication tables resident and reuse delta nibbles in AVX2 and AVX512BW REC2	2026-08-21 12:06:25 +02:00
Andrea Mazzoleni	b5d507fbe9	Use primitive generator 3 for AES Cauchy mode	2026-08-21 12:06:25 +02:00
Andrea Mazzoleni	47b321d97c	Support dynamic runtime selection of RAID AES mode	2026-08-18 23:33:56 +02:00
Andrea Mazzoleni	e43964523f	Refactor and reorganize parity generation functions using inline templates	2026-08-18 23:33:54 +02:00