/* * Copyright (C) 2013 Andrea Mazzoleni * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ /* * The RAID5/RAID6 support was originally derived from the libraid6 library * by H. Peter Anvin released with license "GPL2 or any later version" * used in the Linux Kernel 2.6.38. * This support was later completely rewritten (many times), but the * H. Peter Anvin's Copyright may still apply. * * The RAIDTP/RAIDQP/RAIDPP/RAIDHP support is original work implemented * from scratch. * * The RAID5 and RAID6 support works like the one implemented in the Linux * Kernel RAID and it's based on the Anvin's paper "The mathematics of RAID-6" [1]. * * We compute the parity in the Galois Field GF(2^8) with the primitive * polynomial x^8 + x^4 + x^3 + x^2 + 1 (285 decimal), starting from a set * of n disk Di with 0<=i=0;--d) { p0 ^= v_32(vbuf[d][off]); p1 ^= v_32(vbuf[d][off+4]); } v_32(p[off]) = p0; v_32(p[off+4]) = p1; } } /* * RAID5 64bit C implementation */ void raid5_int64(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; int d, l; unsigned off; uint64_t p0; uint64_t p1; l = data - 1; p = vbuf[data]; for(off=0;off=0;--d) { p0 ^= v_64(vbuf[d][off]); p1 ^= v_64(vbuf[d][off+8]); } v_64(p[off]) = p0; v_64(p[off+8]) = p1; } } #if defined(__i386__) || defined(__x86_64__) /* * RAID5 SSE2 implementation * * Note that we don't have the corresponding x64 sse2ext function using more * registers because processing a block of 64 bytes already fills * the typical cache block, and processing 128 bytes doesn't increase * performance. */ void raid5_sse2(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; int d, l; unsigned off; l = data - 1; p = vbuf[data]; for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm5" : : "m" (vbuf[d][off+16])); asm volatile("movdqa %0,%%xmm6" : : "m" (vbuf[d][off+32])); asm volatile("movdqa %0,%%xmm7" : : "m" (vbuf[d][off+48])); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm7,%xmm3"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (p[off+16])); asm volatile("movntdq %%xmm2,%0" : "=m" (p[off+32])); asm volatile("movntdq %%xmm3,%0" : "=m" (p[off+48])); } asm volatile("sfence" : : : "memory"); } #endif /** * Multiply each byte of a uint32 by 2 in the GF(2^8). */ __attribute__((always_inline)) static inline uint32_t x2_32(uint32_t v) { uint32_t mask = v & 0x80808080U; mask = (mask << 1) - (mask >> 7); v = (v << 1) & 0xfefefefeU; v ^= mask & 0x1d1d1d1dU; return v; } /** * Multiply each byte of a uint64 by 2 in the GF(2^8). */ __attribute__((always_inline)) static inline uint64_t x2_64(uint64_t v) { uint64_t mask = v & 0x8080808080808080ULL; mask = (mask << 1) - (mask >> 7); v = (v << 1) & 0xfefefefefefefefeULL; v ^= mask & 0x1d1d1d1d1d1d1d1dULL; return v; } /* * RAID6 32bit C implementation */ void raid6_int32(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; int d, l; unsigned off; uint32_t d0, q0, p0; uint32_t d1, q1, p1; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; for(off=0;off=0;--d) { d0 = v_32(vbuf[d][off]); d1 = v_32(vbuf[d][off+4]); p0 ^= d0; p1 ^= d1; q0 = x2_32(q0); q1 = x2_32(q1); q0 ^= d0; q1 ^= d1; } v_32(p[off]) = p0; v_32(p[off+4]) = p1; v_32(q[off]) = q0; v_32(q[off+4]) = q1; } } /* * RAID6 64bit C implementation */ void raid6_int64(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; int d, l; unsigned off; uint64_t d0, q0, p0; uint64_t d1, q1, p1; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; for(off=0;off=0;--d) { d0 = v_64(vbuf[d][off]); d1 = v_64(vbuf[d][off+8]); p0 ^= d0; p1 ^= d1; q0 = x2_64(q0); q1 = x2_64(q1); q0 ^= d0; q1 ^= d1; } v_64(p[off]) = p0; v_64(p[off+8]) = p1; v_64(q[off]) = q0; v_64(q[off+8]) = q1; } } #if defined(__i386__) || defined(__x86_64__) static const struct raid_16_const { unsigned char poly[16]; unsigned char mask[16]; } raid_16_const __attribute__((aligned(32))) = { { 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d }, { 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f } }; /* * RAID6 SSE2 implementation */ void raid6_sse2(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.poly[0])); for(off=0;off=0;--d) { asm volatile("pxor %xmm4,%xmm4"); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pcmpgtb %xmm2,%xmm4"); asm volatile("pcmpgtb %xmm3,%xmm5"); asm volatile("paddb %xmm2,%xmm2"); asm volatile("paddb %xmm3,%xmm3"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pand %xmm7,%xmm5"); asm volatile("pxor %xmm4,%xmm2"); asm volatile("pxor %xmm5,%xmm3"); asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm5" : : "m" (vbuf[d][off+16])); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("pxor %xmm4,%xmm2"); asm volatile("pxor %xmm5,%xmm3"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (p[off+16])); asm volatile("movntdq %%xmm2,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (q[off+16])); } asm volatile("sfence" : : : "memory"); } #endif #if defined(__x86_64__) /* * RAID6 SSE2 implementation * * Note that it uses 16 registers, meaning that x64 is required. */ void raid6_sse2ext(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; asm volatile("movdqa %0,%%xmm15" : : "m" (raid_16_const.poly[0])); for(off=0;off=0;--d) { asm volatile("pxor %xmm8,%xmm8"); asm volatile("pxor %xmm9,%xmm9"); asm volatile("pxor %xmm10,%xmm10"); asm volatile("pxor %xmm11,%xmm11"); asm volatile("pcmpgtb %xmm4,%xmm8"); asm volatile("pcmpgtb %xmm5,%xmm9"); asm volatile("pcmpgtb %xmm6,%xmm10"); asm volatile("pcmpgtb %xmm7,%xmm11"); asm volatile("paddb %xmm4,%xmm4"); asm volatile("paddb %xmm5,%xmm5"); asm volatile("paddb %xmm6,%xmm6"); asm volatile("paddb %xmm7,%xmm7"); asm volatile("pand %xmm15,%xmm8"); asm volatile("pand %xmm15,%xmm9"); asm volatile("pand %xmm15,%xmm10"); asm volatile("pand %xmm15,%xmm11"); asm volatile("pxor %xmm8,%xmm4"); asm volatile("pxor %xmm9,%xmm5"); asm volatile("pxor %xmm10,%xmm6"); asm volatile("pxor %xmm11,%xmm7"); asm volatile("movdqa %0,%%xmm8" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm9" : : "m" (vbuf[d][off+16])); asm volatile("movdqa %0,%%xmm10" : : "m" (vbuf[d][off+32])); asm volatile("movdqa %0,%%xmm11" : : "m" (vbuf[d][off+48])); asm volatile("pxor %xmm8,%xmm0"); asm volatile("pxor %xmm9,%xmm1"); asm volatile("pxor %xmm10,%xmm2"); asm volatile("pxor %xmm11,%xmm3"); asm volatile("pxor %xmm8,%xmm4"); asm volatile("pxor %xmm9,%xmm5"); asm volatile("pxor %xmm10,%xmm6"); asm volatile("pxor %xmm11,%xmm7"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (p[off+16])); asm volatile("movntdq %%xmm2,%0" : "=m" (p[off+32])); asm volatile("movntdq %%xmm3,%0" : "=m" (p[off+48])); asm volatile("movntdq %%xmm4,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm5,%0" : "=m" (q[off+16])); asm volatile("movntdq %%xmm6,%0" : "=m" (q[off+32])); asm volatile("movntdq %%xmm7,%0" : "=m" (q[off+48])); } asm volatile("sfence" : : : "memory"); } #endif /* * RAIDTP 8bit C implementation * * Note that instead of a generic multiplicationt table, likely resulting in multiple cache misses, * a precomputed table could be used. But this is only a kind of reference function, * and we are not really interested on speed. */ void raidTP_int8(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; int d, l; unsigned off; uint8_t d0, r0, q0, p0; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; for(off=0;off=0;--d) { d0 = v_8(vbuf[d][off]); p0 ^= d0; q0 ^= gfmul[d0][gfmatrix[1][d]]; r0 ^= gfmul[d0][gfmatrix[2][d]]; } v_8(p[off]) = p0; v_8(q[off]) = q0; v_8(r[off]) = r0; } } #if defined(__i386__) || defined(__x86_64__) /* * RAIDTP SSSE3 implementation */ void raidTP_ssse3(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; asm volatile("movdqa %0,%%xmm3" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.mask[0])); for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pcmpgtb %xmm1,%xmm5"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("pand %xmm3,%xmm5"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm4,%xmm1"); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("psraw $4,%xmm5"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pand %xmm7,%xmm5"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm5,%xmm6"); asm volatile("pxor %xmm6,%xmm2"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); } asm volatile("sfence" : : : "memory"); } #endif #if defined(__x86_64__) /* * RAIDTP SSSE3 implementation * * Note that it uses 16 registers, meaning that x64 is required. */ void raidTP_ssse3ext(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; asm volatile("movdqa %0,%%xmm3" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm11" : : "m" (raid_16_const.mask[0])); for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm12" : : "m" (vbuf[d][off+16])); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pxor %xmm13,%xmm13"); asm volatile("pcmpgtb %xmm1,%xmm5"); asm volatile("pcmpgtb %xmm9,%xmm13"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("paddb %xmm9,%xmm9"); asm volatile("pand %xmm3,%xmm5"); asm volatile("pand %xmm3,%xmm13"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("pxor %xmm13,%xmm9"); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm4,%xmm1"); asm volatile("pxor %xmm12,%xmm8"); asm volatile("pxor %xmm12,%xmm9"); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("movdqa %xmm12,%xmm13"); asm volatile("psraw $4,%xmm5"); asm volatile("psraw $4,%xmm13"); asm volatile("pand %xmm11,%xmm4"); asm volatile("pand %xmm11,%xmm12"); asm volatile("pand %xmm11,%xmm5"); asm volatile("pand %xmm11,%xmm13"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][0][1][0])); asm volatile("movdqa %xmm6,%xmm14"); asm volatile("movdqa %xmm7,%xmm15"); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm12,%xmm14"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pshufb %xmm13,%xmm15"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm14,%xmm10"); asm volatile("pxor %xmm7,%xmm2"); asm volatile("pxor %xmm15,%xmm10"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm8,%0" : "=m" (p[off+16])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm9,%0" : "=m" (q[off+16])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm10,%0" : "=m" (r[off+16])); } asm volatile("sfence" : : : "memory"); } #endif /* * RAIDQP 8bit C implementation * * Note that instead of a generic multiplicationt table, likely resulting in multiple cache misses, * a precomputed table could be used. But this is only a kind of reference function, * and we are not really interested on speed. */ void raidQP_int8(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; int d, l; unsigned off; uint8_t d0, s0, r0, q0, p0; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; for(off=0;off=0;--d) { d0 = v_8(vbuf[d][off]); p0 ^= d0; q0 ^= gfmul[d0][gfmatrix[1][d]]; r0 ^= gfmul[d0][gfmatrix[2][d]]; s0 ^= gfmul[d0][gfmatrix[3][d]]; } v_8(p[off]) = p0; v_8(q[off]) = q0; v_8(r[off]) = r0; v_8(s[off]) = s0; } } #if defined(__i386__) || defined(__x86_64__) /* * RAIDQP SSSE3 implementation */ void raidQP_ssse3(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pcmpgtb %xmm1,%xmm5"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("pand %xmm7,%xmm5"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.mask[0])); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm4,%xmm1"); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("psraw $4,%xmm5"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pand %xmm7,%xmm5"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm7,%xmm2"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][1][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm3"); asm volatile("pxor %xmm7,%xmm3"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (s[off])); } asm volatile("sfence" : : : "memory"); } #endif #if defined(__x86_64__) /* * RAIDQP SSSE3 implementation * * Note that it uses 16 registers, meaning that x64 is required. */ void raidQP_ssse3ext(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm15" : : "m" (raid_16_const.mask[0])); asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm12" : : "m" (vbuf[d][off+16])); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pxor %xmm13,%xmm13"); asm volatile("pcmpgtb %xmm1,%xmm5"); asm volatile("pcmpgtb %xmm9,%xmm13"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("paddb %xmm9,%xmm9"); asm volatile("pand %xmm7,%xmm5"); asm volatile("pand %xmm7,%xmm13"); asm volatile("pxor %xmm5,%xmm1"); asm volatile("pxor %xmm13,%xmm9"); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm4,%xmm1"); asm volatile("pxor %xmm12,%xmm8"); asm volatile("pxor %xmm12,%xmm9"); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("movdqa %xmm12,%xmm13"); asm volatile("psraw $4,%xmm5"); asm volatile("psraw $4,%xmm13"); asm volatile("pand %xmm15,%xmm4"); asm volatile("pand %xmm15,%xmm12"); asm volatile("pand %xmm15,%xmm5"); asm volatile("pand %xmm15,%xmm13"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][0][1][0])); asm volatile("movdqa %xmm6,%xmm14"); asm volatile("movdqa %xmm7,%xmm15"); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm12,%xmm14"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pshufb %xmm13,%xmm15"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm14,%xmm10"); asm volatile("pxor %xmm7,%xmm2"); asm volatile("pxor %xmm15,%xmm10"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][1][1][0])); asm volatile("movdqa %xmm6,%xmm14"); asm volatile("movdqa %xmm7,%xmm15"); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm12,%xmm14"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pshufb %xmm13,%xmm15"); asm volatile("pxor %xmm6,%xmm3"); asm volatile("pxor %xmm14,%xmm11"); asm volatile("pxor %xmm7,%xmm3"); asm volatile("pxor %xmm15,%xmm11"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm8,%0" : "=m" (p[off+16])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm9,%0" : "=m" (q[off+16])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm10,%0" : "=m" (r[off+16])); asm volatile("movntdq %%xmm3,%0" : "=m" (s[off])); asm volatile("movntdq %%xmm11,%0" : "=m" (s[off+16])); } asm volatile("sfence" : : : "memory"); } #endif /* * RAIDPP 8bit C implementation * * Note that instead of a generic multiplicationt table, likely resulting in multiple cache misses, * a precomputed table could be used. But this is only a kind of reference function, * and we are not really interested on speed. */ void raidPP_int8(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; int d, l; unsigned off; uint8_t d0, t0, s0, r0, q0, p0; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; for(off=0;off=0;--d) { d0 = v_8(vbuf[d][off]); p0 ^= d0; q0 ^= gfmul[d0][gfmatrix[1][d]]; r0 ^= gfmul[d0][gfmatrix[2][d]]; s0 ^= gfmul[d0][gfmatrix[3][d]]; t0 ^= gfmul[d0][gfmatrix[4][d]]; } v_8(p[off]) = p0; v_8(q[off]) = q0; v_8(r[off]) = r0; v_8(s[off]) = s0; v_8(t[off]) = t0; } } #if defined(__i386__) || defined(__x86_64__) /* * RAIDPP SSSE3 implementation */ #ifdef _WIN32 /* ensures that stack is aligned at 16 bytes because we allocate SSE registers in it */ __attribute__((force_align_arg_pointer)) #endif void raidPP_ssse3(unsigned char** vbuf, unsigned data, unsigned size) /* ensures that stack is aligned at 16 bytes because we allocate SSE registers in it */ { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; int d, l; unsigned off; unsigned char p0[16] __attribute__((aligned(16))); l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("movdqa %0,%%xmm6" : : "m" (p0[0])); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.poly[0])); asm volatile("pxor %xmm5,%xmm5"); asm volatile("pcmpgtb %xmm0,%xmm5"); asm volatile("paddb %xmm0,%xmm0"); asm volatile("pand %xmm7,%xmm5"); asm volatile("pxor %xmm5,%xmm0"); asm volatile("pxor %xmm4,%xmm0"); asm volatile("pxor %xmm4,%xmm6"); asm volatile("movdqa %%xmm6,%0" : "=m" (p0)); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.mask[0])); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("psraw $4,%xmm5"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pand %xmm7,%xmm5"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm1"); asm volatile("pxor %xmm7,%xmm1"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][1][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm7,%xmm2"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][2][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][2][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm3"); asm volatile("pxor %xmm7,%xmm3"); } asm volatile("movdqa %0,%%xmm6" : : "m" (p0[0])); asm volatile("movntdq %%xmm6,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm0,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (s[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (t[off])); } asm volatile("sfence" : : : "memory"); } #endif #if defined(__x86_64__) /* * RAIDPP SSSE3 implementation * * Note that it uses 16 registers, meaning that x64 is required. */ void raidPP_ssse3ext(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; asm volatile("movdqa %0,%%xmm14" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm15" : : "m" (raid_16_const.mask[0])); for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm10" : : "m" (vbuf[d][off])); asm volatile("pxor %xmm11,%xmm11"); asm volatile("pcmpgtb %xmm1,%xmm11"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("pand %xmm14,%xmm11"); asm volatile("pxor %xmm11,%xmm1"); asm volatile("pxor %xmm10,%xmm0"); asm volatile("pxor %xmm10,%xmm1"); asm volatile("movdqa %xmm10,%xmm11"); asm volatile("psraw $4,%xmm11"); asm volatile("pand %xmm15,%xmm10"); asm volatile("pand %xmm15,%xmm11"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm2"); asm volatile("pxor %xmm13,%xmm2"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][1][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm3"); asm volatile("pxor %xmm13,%xmm3"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][2][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][2][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm4"); asm volatile("pxor %xmm13,%xmm4"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (s[off])); asm volatile("movntdq %%xmm4,%0" : "=m" (t[off])); } asm volatile("sfence" : : : "memory"); } #endif /* * RAIDHP 8bit C implementation * * Note that instead of a generic multiplicationt table, likely resulting in multiple cache misses, * a precomputed table could be used. But this is only a kind of reference function, * and we are not really interested on speed. */ void raidHP_int8(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; unsigned char* o; int d, l; unsigned off; uint8_t d0, u0, t0, s0, r0, q0, p0; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; o = vbuf[data+5]; for(off=0;off=0;--d) { d0 = v_8(vbuf[d][off]); p0 ^= d0; q0 ^= gfmul[d0][gfmatrix[1][d]]; r0 ^= gfmul[d0][gfmatrix[2][d]]; s0 ^= gfmul[d0][gfmatrix[3][d]]; t0 ^= gfmul[d0][gfmatrix[4][d]]; u0 ^= gfmul[d0][gfmatrix[5][d]]; } v_8(p[off]) = p0; v_8(q[off]) = q0; v_8(r[off]) = r0; v_8(s[off]) = s0; v_8(t[off]) = t0; v_8(o[off]) = u0; } } #if defined(__i386__) || defined(__x86_64__) /* * RAIDHP SSSE3 implementation */ #ifdef _WIN32 /* ensures that stack is aligned at 16 bytes because we allocate SSE registers in it */ __attribute__((force_align_arg_pointer)) #endif void raidHP_ssse3(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; unsigned char* o; int d, l; unsigned off; unsigned char p0[16] __attribute__((aligned(16))); unsigned char q0[16] __attribute__((aligned(16))); l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; o = vbuf[data+5]; for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm5" : : "m" (p0[0])); asm volatile("movdqa %0,%%xmm6" : : "m" (q0[0])); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.poly[0])); asm volatile("pxor %xmm4,%xmm4"); asm volatile("pcmpgtb %xmm6,%xmm4"); asm volatile("paddb %xmm6,%xmm6"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pxor %xmm4,%xmm6"); asm volatile("movdqa %0,%%xmm4" : : "m" (vbuf[d][off])); asm volatile("pxor %xmm4,%xmm5"); asm volatile("pxor %xmm4,%xmm6"); asm volatile("movdqa %%xmm5,%0" : "=m" (p0)); asm volatile("movdqa %%xmm6,%0" : "=m" (q0)); asm volatile("movdqa %0,%%xmm7" : : "m" (raid_16_const.mask[0])); asm volatile("movdqa %xmm4,%xmm5"); asm volatile("psraw $4,%xmm5"); asm volatile("pand %xmm7,%xmm4"); asm volatile("pand %xmm7,%xmm5"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm0"); asm volatile("pxor %xmm7,%xmm0"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][1][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm1"); asm volatile("pxor %xmm7,%xmm1"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][2][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][2][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm2"); asm volatile("pxor %xmm7,%xmm2"); asm volatile("movdqa %0,%%xmm6" : : "m" (gfpshufb[d][3][0][0])); asm volatile("movdqa %0,%%xmm7" : : "m" (gfpshufb[d][3][1][0])); asm volatile("pshufb %xmm4,%xmm6"); asm volatile("pshufb %xmm5,%xmm7"); asm volatile("pxor %xmm6,%xmm3"); asm volatile("pxor %xmm7,%xmm3"); } asm volatile("movdqa %0,%%xmm5" : : "m" (p0[0])); asm volatile("movdqa %0,%%xmm6" : : "m" (q0[0])); asm volatile("movntdq %%xmm5,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm6,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm0,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (s[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (t[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (o[off])); } asm volatile("sfence" : : : "memory"); } #endif #if defined(__x86_64__) /* * RAIDHP SSSE3 implementation * * Note that it uses 16 registers, meaning that x64 is required. */ void raidHP_ssse3ext(unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; unsigned char* o; int d, l; unsigned off; l = data - 1; p = vbuf[data]; q = vbuf[data+1]; r = vbuf[data+2]; s = vbuf[data+3]; t = vbuf[data+4]; o = vbuf[data+5]; asm volatile("movdqa %0,%%xmm14" : : "m" (raid_16_const.poly[0])); asm volatile("movdqa %0,%%xmm15" : : "m" (raid_16_const.mask[0])); for(off=0;off=0;--d) { asm volatile("movdqa %0,%%xmm10" : : "m" (vbuf[d][off])); asm volatile("pxor %xmm11,%xmm11"); asm volatile("pcmpgtb %xmm1,%xmm11"); asm volatile("paddb %xmm1,%xmm1"); asm volatile("pand %xmm14,%xmm11"); asm volatile("pxor %xmm11,%xmm1"); asm volatile("pxor %xmm10,%xmm0"); asm volatile("pxor %xmm10,%xmm1"); asm volatile("movdqa %xmm10,%xmm11"); asm volatile("psraw $4,%xmm11"); asm volatile("pand %xmm15,%xmm10"); asm volatile("pand %xmm15,%xmm11"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][0][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][0][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm2"); asm volatile("pxor %xmm13,%xmm2"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][1][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][1][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm3"); asm volatile("pxor %xmm13,%xmm3"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][2][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][2][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm4"); asm volatile("pxor %xmm13,%xmm4"); asm volatile("movdqa %0,%%xmm12" : : "m" (gfpshufb[d][3][0][0])); asm volatile("movdqa %0,%%xmm13" : : "m" (gfpshufb[d][3][1][0])); asm volatile("pshufb %xmm10,%xmm12"); asm volatile("pshufb %xmm11,%xmm13"); asm volatile("pxor %xmm12,%xmm5"); asm volatile("pxor %xmm13,%xmm5"); } asm volatile("movntdq %%xmm0,%0" : "=m" (p[off])); asm volatile("movntdq %%xmm1,%0" : "=m" (q[off])); asm volatile("movntdq %%xmm2,%0" : "=m" (r[off])); asm volatile("movntdq %%xmm3,%0" : "=m" (s[off])); asm volatile("movntdq %%xmm4,%0" : "=m" (t[off])); asm volatile("movntdq %%xmm5,%0" : "=m" (o[off])); } asm volatile("sfence" : : : "memory"); } #endif /****************************************************************************/ /* parity generation */ /* internal forwarder */ static void (*raid5_gen)(unsigned char** vbuf, unsigned data, unsigned size); static void (*raid6_gen)(unsigned char** vbuf, unsigned data, unsigned size); static void (*raidTP_gen)(unsigned char** vbuf, unsigned data, unsigned size); static void (*raidQP_gen)(unsigned char** vbuf, unsigned data, unsigned size); static void (*raidPP_gen)(unsigned char** vbuf, unsigned data, unsigned size); static void (*raidHP_gen)(unsigned char** vbuf, unsigned data, unsigned size); void raid_gen(unsigned level, unsigned char** vbuf, unsigned data, unsigned size) { switch (level) { case 1 : raid5_gen(vbuf, data, size); break; case 2 : raid6_gen(vbuf, data, size); break; case 3 : raidTP_gen(vbuf, data, size); break; case 4 : raidQP_gen(vbuf, data, size); break; case 5 : raidPP_gen(vbuf, data, size); break; case 6 : raidHP_gen(vbuf, data, size); break; default: fprintf(stderr, "Invalid raid gen level\n"); exit(EXIT_FAILURE); } } /****************************************************************************/ /* recovering */ /** * GF a*b. */ static inline unsigned char mul(unsigned char a, unsigned char b) { return gfmul[a][b]; } /** * GF 1/a. * Not defined for a == 0. */ static inline unsigned char inv(unsigned char v) { if (v == 0) { fprintf(stderr, "GF division by zero\n"); exit(EXIT_FAILURE); } return gfinv[v]; } /** * GF 2^a. */ static inline unsigned char pow2(int v) { if (v < 0 || v > 254) { fprintf(stderr, "GF invalid exponent\n"); exit(EXIT_FAILURE); } return gfexp2[v]; } /** * Gets the multiplication table for a specified value. */ static inline const unsigned char* table(unsigned char v) { return gfmul[v]; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_1data(int x, int i, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* pa; /* parity buffer */ p = vbuf[data+i]; /* missing data blcks */ pa = vbuf[x]; /* set at zero the missing data blocks */ vbuf[x] = zero; /* compute only for the level we really need */ vbuf[data+i] = pa; /* compute the parity */ raid_gen(i + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[data+i] = p; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_2data(unsigned int x, int y, int i, int j, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* pa; unsigned char* qa; /* parity buffer */ p = vbuf[data+i]; q = vbuf[data+j]; /* missing data blocks */ pa = vbuf[x]; qa = vbuf[y]; /* set at zero the missing data blocks */ vbuf[x] = zero; vbuf[y] = zero; /* compute the parity over the missing data blocks */ vbuf[data+i] = pa; vbuf[data+j] = qa; /* compute only for the level we really need */ raid_gen(j + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[y] = qa; vbuf[data+i] = p; vbuf[data+j] = q; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_3data(unsigned int x, int y, int z, int i, int j, int k, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* pa; unsigned char* qa; unsigned char* ra; /* parity buffer */ p = vbuf[data+i]; q = vbuf[data+j]; r = vbuf[data+k]; /* missing data blocks */ pa = vbuf[x]; qa = vbuf[y]; ra = vbuf[z]; /* set at zero the missing data blocks */ vbuf[x] = zero; vbuf[y] = zero; vbuf[z] = zero; /* compute the parity over the missing data blocks */ vbuf[data+i] = pa; vbuf[data+j] = qa; vbuf[data+k] = ra; /* compute only for the level we really need */ raid_gen(k + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[y] = qa; vbuf[z] = ra; vbuf[data+i] = p; vbuf[data+j] = q; vbuf[data+k] = r; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_4data(unsigned int x, int y, int z, int v, int i, int j, int k, int l, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* pa; unsigned char* qa; unsigned char* ra; unsigned char* sa; /* parity buffer */ p = vbuf[data+i]; q = vbuf[data+j]; r = vbuf[data+k]; s = vbuf[data+l]; /* missing data blocks */ pa = vbuf[x]; qa = vbuf[y]; ra = vbuf[z]; sa = vbuf[v]; /* set at zero the missing data blocks */ vbuf[x] = zero; vbuf[y] = zero; vbuf[z] = zero; vbuf[v] = zero; /* compute the parity over the missing data blocks */ vbuf[data+i] = pa; vbuf[data+j] = qa; vbuf[data+k] = ra; vbuf[data+l] = sa; /* compute only for the level we really need */ raid_gen(l + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[y] = qa; vbuf[z] = ra; vbuf[v] = sa; vbuf[data+i] = p; vbuf[data+j] = q; vbuf[data+k] = r; vbuf[data+l] = s; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_5data(unsigned int x, int y, int z, int v, int u, int i, int j, int k, int l, int m, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; unsigned char* pa; unsigned char* qa; unsigned char* ra; unsigned char* sa; unsigned char* ta; /* parity buffer */ p = vbuf[data+i]; q = vbuf[data+j]; r = vbuf[data+k]; s = vbuf[data+l]; t = vbuf[data+m]; /* missing data blocks */ pa = vbuf[x]; qa = vbuf[y]; ra = vbuf[z]; sa = vbuf[v]; ta = vbuf[u]; /* set at zero the missing data blocks */ vbuf[x] = zero; vbuf[y] = zero; vbuf[z] = zero; vbuf[v] = zero; vbuf[u] = zero; /* compute the parity over the missing data blocks */ vbuf[data+i] = pa; vbuf[data+j] = qa; vbuf[data+k] = ra; vbuf[data+l] = sa; vbuf[data+m] = ta; /* compute only for the level we really need */ raid_gen(m + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[y] = qa; vbuf[z] = ra; vbuf[v] = sa; vbuf[u] = ta; vbuf[data+i] = p; vbuf[data+j] = q; vbuf[data+k] = r; vbuf[data+l] = s; vbuf[data+m] = t; } /** * Computes the parity without the missing data blocks * and store it in the buffers of such data blocks. */ static void raid_delta_6data(unsigned int x, int y, int z, int v, int u, int w, int i, int j, int k, int l, int m, int n, unsigned char** vbuf, unsigned data, unsigned char* zero, unsigned size) { unsigned char* p; unsigned char* q; unsigned char* r; unsigned char* s; unsigned char* t; unsigned char* o; unsigned char* pa; unsigned char* qa; unsigned char* ra; unsigned char* sa; unsigned char* ta; unsigned char* oa; /* parity buffer */ p = vbuf[data+i]; q = vbuf[data+j]; r = vbuf[data+k]; s = vbuf[data+l]; t = vbuf[data+m]; o = vbuf[data+n]; /* missing data blocks */ pa = vbuf[x]; qa = vbuf[y]; ra = vbuf[z]; sa = vbuf[v]; ta = vbuf[u]; oa = vbuf[w]; /* set at zero the missing data blocks */ vbuf[x] = zero; vbuf[y] = zero; vbuf[z] = zero; vbuf[v] = zero; vbuf[u] = zero; vbuf[w] = zero; /* compute the parity over the missing data blocks */ vbuf[data+i] = pa; vbuf[data+j] = qa; vbuf[data+k] = ra; vbuf[data+l] = sa; vbuf[data+m] = ta; vbuf[data+n] = oa; /* compute only for the level we really need */ raid_gen(n + 1, vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[y] = qa; vbuf[z] = ra; vbuf[v] = sa; vbuf[u] = ta; vbuf[w] = oa; vbuf[data+i] = p; vbuf[data+j] = q; vbuf[data+k] = r; vbuf[data+l] = s; vbuf[data+m] = t; vbuf[data+n] = o; } /****************************************************************************/ /* specialized raid recovering */ /** * Recover failure of one data block for RAID5. * * Starting from the equation: * * Pd = Dx * * and solving we get: * * Dx = Pd (this one is easy :D) */ static void raid5_recov_data(int x, unsigned char** vbuf, unsigned data, unsigned size) { unsigned char* p; unsigned char* pa; /* for RAID5 we can directly compute the mssing block */ /* and we don't need to use the zero buffer */ p = vbuf[data]; pa = vbuf[x]; /* use the parity as missing data block */ vbuf[x] = p; /* compute the parity over the missing data block */ vbuf[data] = pa; /* compute */ raid5_gen(vbuf, data, size); /* restore as before */ vbuf[x] = pa; vbuf[data] = p; } /** * Recover failure of two data blocks for RAID6. * * Starting from the equations: * * Pd = Dx + Dy * Qd = 2^x * Dx + 2^y * Dy * * and solving we get: * * 1 2^(-x) * Dy = ----------- * Pd + ----------- * Qd * 2^(y-x) + 1 2^(y-x) + 1 * * Dx = Dy + Pd * * with conditions: * * 2^x != 0 * 2^(y-x) + 1 != 0 * * That are always satisfied for any 0<=xname != 0) { if (i->p == func) return i->name; ++i; } return "unknown"; } const char* raid5_tag(void) { return raid_tag(raid5_gen); } const char* raid6_tag(void) { return raid_tag(raid6_gen); } const char* raidTP_tag(void) { return raid_tag(raidTP_gen); } const char* raidQP_tag(void) { return raid_tag(raidQP_gen); } const char* raidPP_tag(void) { return raid_tag(raidPP_gen); } const char* raidHP_tag(void) { return raid_tag(raidHP_gen); }