mirror of
https://github.com/amadvance/snapraid.git
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08831c6641
Uses Murmur3 as default hash. Check now returns and error even if only recoverable errors are present.
331 lines
9.1 KiB
C
331 lines
9.1 KiB
C
/*
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* Copyright (C) 2011 Andrea Mazzoleni
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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#include "portable.h"
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#include "raid.h"
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#include "cpu.h"
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/*
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* 2-way unrolled portable integer math RAID-5 instruction set
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*/
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void raid5_int32r2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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int z, z0;
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unsigned d;
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uint32_t wp0;
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uint32_t wp1;
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z0 = diskmax - 2; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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for(d=0;d<block_size;d+=8) {
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wp0 = *(uint32_t *)&dptr[z0][d+0*4];
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wp1 = *(uint32_t *)&dptr[z0][d+1*4];
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for(z=z0-1;z>=0;--z) {
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wp0 ^= *(uint32_t *)&dptr[z][d+0*4];
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wp1 ^= *(uint32_t *)&dptr[z][d+1*4];
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}
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*(uint32_t *)&p[d+4*0] = wp0;
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*(uint32_t *)&p[d+4*1] = wp1;
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}
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}
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/*
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* Unrolled-by-2 MMX implementation
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*/
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void raid5_mmxr2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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int z, z0;
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unsigned d;
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z0 = diskmax - 2; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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for(d=0;d<block_size;d+=16) {
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d]));
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asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8]));
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for(z=z0-1;z>=0;--z) {
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asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d]));
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asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8]));
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asm volatile("pxor %mm5,%mm2");
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asm volatile("pxor %mm7,%mm3");
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}
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asm volatile("movq %%mm2,%0" : "=m" (p[d]));
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asm volatile("movq %%mm3,%0" : "=m" (p[d+8]));
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}
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asm volatile("emms" : : : "memory");
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}
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void raid5_sse2r2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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int z, z0;
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unsigned d;
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z0 = diskmax - 2; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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for(d=0;d<block_size;d+=32) {
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asm volatile("movdqa %0,%%xmm2" : : "m" (dptr[z0][d]));
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asm volatile("movdqa %0,%%xmm3" : : "m" (dptr[z0][d+16]));
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for(z=z0-1;z>=0;--z) {
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asm volatile("movdqa %0,%%xmm5" : : "m" (dptr[z][d]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (dptr[z][d+16]));
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asm volatile("pxor %xmm5,%xmm2");
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asm volatile("pxor %xmm7,%xmm3");
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}
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+16]));
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}
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asm volatile("sfence" : : : "memory");
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}
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/*
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* Repeats an 8 bit nibble to a full 32 bits value.
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*/
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#define NBYTES(x) ((x) * 0x01010101U)
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/*
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* These sub-operations are separate inlines since they can sometimes be
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* specially optimized using architecture-specific hacks.
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*/
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/*
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* The SHLBYTE() operation shifts each byte left by 1, *not*
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* rolling over into the next byte.
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*/
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static inline uint32_t SHLBYTE(uint32_t v)
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{
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uint32_t vv;
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vv = (v << 1) & NBYTES(0xfe);
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return vv;
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}
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/*
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* The MASK() operation returns 0xFF in any byte for which the high
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* bit is 1, 0x00 for any byte for which the high bit is 0.
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*/
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static inline uint32_t MASK(uint32_t v)
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{
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uint32_t vv;
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vv = v & NBYTES(0x80);
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vv = (vv << 1) - (vv >> 7); /* Overflow on the top bit is OK */
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return vv;
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}
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/*
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* 2-way unrolled portable integer math RAID-6 instruction set
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*/
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void raid6_int32r2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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unsigned char* q;
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int z, z0;
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unsigned d;
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uint32_t wd0, wq0, wp0, w10, w20;
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uint32_t wd1, wq1, wp1, w11, w21;
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z0 = diskmax - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS qarity */
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for(d=0;d<block_size;d+=8) {
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wq0 = wp0 = *(uint32_t *)&dptr[z0][d+0*4];
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wq1 = wp1 = *(uint32_t *)&dptr[z0][d+1*4];
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for (z=z0-1;z>= 0;--z) {
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wd0 = *(uint32_t *)&dptr[z][d+0*4];
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wd1 = *(uint32_t *)&dptr[z][d+1*4];
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wp0 ^= wd0;
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wp1 ^= wd1;
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w20 = MASK(wq0);
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w21 = MASK(wq1);
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w10 = SHLBYTE(wq0);
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w11 = SHLBYTE(wq1);
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w20 &= NBYTES(0x1d);
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w21 &= NBYTES(0x1d);
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w10 ^= w20;
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w11 ^= w21;
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wq0 = w10 ^ wd0;
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wq1 = w11 ^ wd1;
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}
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*(uint32_t *)&p[d+4*0] = wp0;
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*(uint32_t *)&p[d+4*1] = wp1;
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*(uint32_t *)&q[d+4*0] = wq0;
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*(uint32_t *)&q[d+4*1] = wq1;
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}
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}
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#if defined(__i386__) || defined(__x86_64__)
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static const struct raid6_mmx_constants {
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uint64_t x1d;
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} raid6_mmx_constants = {
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0x1d1d1d1d1d1d1d1dULL,
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};
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/*
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* Unrolled-by-2 MMX implementation
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*/
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void raid6_mmxr2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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unsigned char* q;
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int z, z0;
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unsigned d;
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z0 = diskmax - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS qarity */
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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asm volatile("pxor %mm7,%mm7"); /* Zero temp */
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for(d=0;d<block_size;d+=16) {
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d]));
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asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8]));
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asm volatile("movq %mm2,%mm4");
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asm volatile("movq %mm3,%mm6");
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for(z=z0-1;z>=0;--z) {
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asm volatile("pcmpgtb %mm4,%mm5");
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asm volatile("pcmpgtb %mm6,%mm7");
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asm volatile("paddb %mm4,%mm4");
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asm volatile("paddb %mm6,%mm6");
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asm volatile("pand %mm0,%mm5");
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asm volatile("pand %mm0,%mm7");
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asm volatile("pxor %mm5,%mm4");
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asm volatile("pxor %mm7,%mm6");
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asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d]));
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asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8]));
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asm volatile("pxor %mm5,%mm2");
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asm volatile("pxor %mm7,%mm3");
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asm volatile("pxor %mm5,%mm4");
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asm volatile("pxor %mm7,%mm6");
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asm volatile("pxor %mm5,%mm5");
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asm volatile("pxor %mm7,%mm7");
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}
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asm volatile("movq %%mm2,%0" : "=m" (p[d]));
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asm volatile("movq %%mm3,%0" : "=m" (p[d+8]));
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asm volatile("movq %%mm4,%0" : "=m" (q[d]));
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asm volatile("movq %%mm6,%0" : "=m" (q[d+8]));
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}
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asm volatile("emms" : : : "memory");
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}
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static const struct raid6_sse_constants {
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uint64_t x1d[2];
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} raid6_sse_constants __attribute__((aligned(16))) = {
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{ 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL },
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};
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/*
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* Unrolled-by-2 SSE2 implementation
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*/
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void raid6_sse2r2(unsigned char** dptr, unsigned diskmax, unsigned block_size)
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{
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unsigned char* p;
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unsigned char* q;
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int z, z0;
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unsigned d;
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z0 = diskmax - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS qarity */
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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asm volatile("pxor %xmm7,%xmm7"); /* Zero temp */
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/* We uniformly assume a single prefetch covers at least 32 bytes */
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for(d=0;d<block_size;d+=32) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("movdqa %0,%%xmm2" : : "m" (dptr[z0][d])); /* P[0] */
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asm volatile("movdqa %0,%%xmm3" : : "m" (dptr[z0][d+16])); /* P[1] */
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asm volatile("movdqa %xmm2,%xmm4"); /* Q[0] */
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asm volatile("movdqa %xmm3,%xmm6"); /* Q[1] */
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for(z=z0-1;z>=0;--z) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("pcmpgtb %xmm6,%xmm7");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("paddb %xmm6,%xmm6");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pand %xmm0,%xmm7");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("movdqa %0,%%xmm5" : : "m" (dptr[z][d]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (dptr[z][d+16]));
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asm volatile("pxor %xmm5,%xmm2");
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asm volatile("pxor %xmm7,%xmm3");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm7,%xmm7");
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}
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+16]));
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asm volatile("movntdq %%xmm4,%0" : "=m" (q[d]));
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+16]));
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}
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asm volatile("sfence" : : : "memory");
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}
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#endif
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void (*raid5_gen)(unsigned char** dptr, unsigned diskmax, unsigned block_size);
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void (*raid6_gen)(unsigned char** dptr, unsigned diskmax, unsigned block_size);
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void raid_init(void)
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{
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raid5_gen = raid5_int32r2;
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raid6_gen = raid6_int32r2;
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#if defined(__i386__) || defined(__x86_64__)
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/*
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if (cpu_has_mmx()) {
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raid5_gen = raid5_mmxr2;
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raid6_gen = raid6_mmxr2;
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}
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if (cpu_has_sse2()) {
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raid5_gen = raid5_sse2r2;
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raid6_gen = raid6_sse2r2;
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}
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*/
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#endif
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}
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