mirror of
https://github.com/amadvance/snapraid.git
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269 lines
7.3 KiB
C
269 lines
7.3 KiB
C
/*
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* Copyright (C) 2013 Andrea Mazzoleni
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __RAID_CPU_H
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#define __RAID_CPU_H
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#ifdef CONFIG_X86
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static inline void raid_cpuid(uint32_t func_eax, uint32_t sub_ecx, uint32_t *reg)
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{
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asm volatile (
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#if defined(__i386__) && defined(__PIC__)
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/* allow compilation in PIC mode saving ebx */
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"xchgl %%ebx, %1\n"
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"cpuid\n"
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"xchgl %%ebx, %1\n"
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: "=a" (reg[0]), "=r" (reg[1]), "=c" (reg[2]), "=d" (reg[3])
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: "0" (func_eax), "2" (sub_ecx)
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#else
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"cpuid\n"
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: "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3])
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: "0" (func_eax), "2" (sub_ecx)
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#endif
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);
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}
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static inline void raid_xgetbv(uint32_t* reg)
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{
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/* get the value of the Extended Control Register ecx=0 */
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asm volatile (
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/* uses a direct encoding of the XGETBV instruction as only recent */
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/* assemblers support it. */
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/* the next line is equivalent at: "xgetbv\n" */
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".byte 0x0f, 0x01, 0xd0\n"
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: "=a" (reg[0]), "=d" (reg[3])
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: "c" (0)
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);
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}
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#define CPU_VENDOR_MAX 13
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static inline void raid_cpu_info(char *vendor, unsigned *family, unsigned *model)
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{
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uint32_t reg[4];
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unsigned f, ef, m, em;
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raid_cpuid(0, 0, reg);
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((uint32_t*)vendor)[0] = reg[1];
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((uint32_t*)vendor)[1] = reg[3];
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((uint32_t*)vendor)[2] = reg[2];
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vendor[12] = 0;
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raid_cpuid(1, 0, reg);
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f = (reg[0] >> 8) & 0xF;
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ef = (reg[0] >> 20) & 0xFF;
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m = (reg[0] >> 4) & 0xF;
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em = (reg[0] >> 16) & 0xF;
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if (strcmp(vendor, "AuthenticAMD") == 0) {
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if (f < 15) {
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*family = f;
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*model = m;
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} else {
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*family = f + ef;
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*model = m + (em << 4);
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}
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} else {
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*family = f + ef;
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*model = m + (em << 4);
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}
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}
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static inline int raid_cpu_match_sse(uint32_t cpuid_1_ecx, uint32_t cpuid_1_edx)
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{
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uint32_t reg[4];
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raid_cpuid(1, 0, reg);
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if ((reg[2] & cpuid_1_ecx) != cpuid_1_ecx)
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return 0;
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if ((reg[3] & cpuid_1_edx) != cpuid_1_edx)
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return 0;
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return 1;
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}
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static inline int raid_cpu_match_avx(uint32_t cpuid_1_ecx, uint32_t cpuid_7_ebx, uint32_t xcr0)
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{
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uint32_t reg[4];
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raid_cpuid(1, 0, reg);
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if ((reg[2] & cpuid_1_ecx) != cpuid_1_ecx)
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return 0;
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raid_xgetbv(reg);
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if ((reg[0] & xcr0) != xcr0)
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return 0;
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raid_cpuid(7, 0, reg);
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if ((reg[1] & cpuid_7_ebx) != cpuid_7_ebx)
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return 0;
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return 1;
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}
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static inline int raid_cpu_has_sse2(void)
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{
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/*
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* Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 11.6.2 Checking for SSE/SSE2 Support
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* Before an application attempts to use the SSE and/or SSE2 extensions, it should check
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* that they are present on the processor:
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* 1. Check that the processor supports the CPUID instruction. Bit 21 of the EFLAGS
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* register can be used to check processor's support the CPUID instruction.
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* 2. Check that the processor supports the SSE and/or SSE2 extensions (true if
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* CPUID.01H:EDX.SSE[bit 25] = 1 and/or CPUID.01H:EDX.SSE2[bit 26] = 1).
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*/
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return raid_cpu_match_sse(
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0,
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1 << 26); /* SSE2 */
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}
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static inline int raid_cpu_has_ssse3(void)
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{
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/*
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* Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 12.7.2 Checking for SSSE3 Support
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* Before an application attempts to use the SSSE3 extensions, the application should
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* follow the steps illustrated in Section 11.6.2, "Checking for SSE/SSE2 Support."
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* Next, use the additional step provided below:
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* Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
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*/
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return raid_cpu_match_sse(
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1 << 9, /* SSSE3 */
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1 << 26); /* SSE2 */
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}
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static inline int raid_cpu_has_crc32(void)
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{
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/*
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* Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 12.12.3 Checking for SSE4.2 Support
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* ...
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* Before an application attempts to use the CRC32 instruction, it must check
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* that the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1).
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*/
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return raid_cpu_match_sse(
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1 << 20, /* CRC32 */
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0);
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}
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static inline int raid_cpu_has_avx2(void)
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{
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/*
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* Intel Architecture Instruction Set Extensions Programming Reference
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* 319433-022 October 2014
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*
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* 14.3 Detection of AVX instructions
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* 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)
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* 2) Issue XGETBV and verify that XCR0[2:1] = `11b' (XMM state and YMM state are enabled by OS).
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* 3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
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* (Step 3 can be done in any order relative to 1 and 2)
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*
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* 14.7.1 Detection of AVX2
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* Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.
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* Application Software must identify that hardware supports AVX, after that it must
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* also detect support for AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5].
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*/
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return raid_cpu_match_avx(
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(1 << 27) | (1 << 28), /* OSXSAVE and AVX */
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1 << 5, /* AVX2 */
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3 << 1); /* OS saves XMM and YMM registers */
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}
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static inline int raid_cpu_has_avx512bw(void)
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{
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/*
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* Intel Architecture Instruction Set Extensions Programming Reference
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* 319433-022 October 2014
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*
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* 2.2 Detection of 512-bit Instruction Groups of Intel AVX-512 Family
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* 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use)
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* 2) Execute XGETBV and verify that XCR0[7:5] = `111b' (OPMASK state, upper 256-bit of
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* ZMM0-ZMM15 and ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = `11b'
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* (XMM state and YMM state are enabled by OS).
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* 3) Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512BW[bit 30] = 1.
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*/
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/* note that intentionally we don't check for AVX and AVX2 */
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/* because the documentation doesn't require that */
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return raid_cpu_match_avx(
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1 << 27, /* XSAVE/XGETBV */
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(1 << 16) | (1 << 30), /* AVX512F and AVX512BW */
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(3 << 1) | (7 << 5)); /* OS saves XMM, YMM and ZMM registers */
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}
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/**
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* Check if the processor has a slow MULT implementation.
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* If yes, it's better to use a hash not based on multiplication.
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*/
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static inline int raid_cpu_has_slowmult(void)
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{
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char vendor[CPU_VENDOR_MAX];
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unsigned family;
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unsigned model;
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raid_cpu_info(vendor, &family, &model);
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if (strcmp(vendor, "GenuineIntel") == 0) {
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/*
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* Intel Atom
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* Murmur3 based on MUL instruction, is a lot slower
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* than Spooky2 based on SHIFTs.
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* Like: 378 MB/s vs 3413 MB/s
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*/
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if (family == 6 && model == 28)
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return 1;
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}
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return 0;
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}
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/**
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* Check if the processor has a slow extended set of SSE registers.
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* If yes, it's better to limit the unroll to the firsrt 8 registers.
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*/
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static inline int raid_cpu_has_slowextendedreg(void)
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{
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char vendor[CPU_VENDOR_MAX];
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unsigned family;
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unsigned model;
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raid_cpu_info(vendor, &family, &model);
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if (strcmp(vendor, "AuthenticAMD") == 0) {
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/*
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* AMD Bulldozer
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* PAR1/PAR2 implementations using 16 SSE registers are slower
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* than ones using only the first 8 registers.
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* Like: 4465 MB/s vs 4922 MB/s.
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*/
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if (family == 21)
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return 1;
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}
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return 0;
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}
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#endif
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#endif
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