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<title>LCOV - lcov.info - raid/cpu.h</title>
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<tr><td class="title">LCOV - code coverage report</td></tr>
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<td width="10%" class="headerItem">Current view:</td>
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<td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">raid</a> - cpu.h<span style="font-size: 80%;"> (source / <a href="cpu.h.func.html">functions</a>)</span></td>
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<td width="15%"></td>
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<td width="10%" class="headerCovTableHead">Hit</td>
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<td width="10%" class="headerCovTableHead">Total</td>
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<td width="15%" class="headerCovTableHead">Coverage</td>
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</tr>
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<tr>
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<td class="headerItem">Test:</td>
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<td class="headerValue">lcov.info</td>
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<td></td>
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<td class="headerItem">Lines:</td>
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<td class="headerCovTableEntry">64</td>
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<td class="headerCovTableEntry">76</td>
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<td class="headerCovTableEntryMed">84.2 %</td>
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</tr>
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<tr>
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<td class="headerItem">Date:</td>
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<td class="headerValue">2016-11-21</td>
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<td></td>
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<td class="headerItem">Functions:</td>
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<td class="headerCovTableEntry">12</td>
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<td class="headerCovTableEntry">12</td>
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<td class="headerCovTableEntryHi">100.0 %</td>
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</tr>
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<tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
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</table>
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</td>
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<tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
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</table>
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<table cellpadding=0 cellspacing=0 border=0>
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<tr>
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<td><br></td>
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</tr>
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<tr>
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<td>
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<pre class="sourceHeading"> Line data Source code</pre>
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<pre class="source">
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<a name="1"><span class="lineNum"> 1 </span> : /*</a>
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<span class="lineNum"> 2 </span> : * Copyright (C) 2013 Andrea Mazzoleni
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<span class="lineNum"> 3 </span> : *
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<span class="lineNum"> 4 </span> : * This program is free software: you can redistribute it and/or modify
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<span class="lineNum"> 5 </span> : * it under the terms of the GNU General Public License as published by
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<span class="lineNum"> 6 </span> : * the Free Software Foundation, either version 2 of the License, or
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<span class="lineNum"> 7 </span> : * (at your option) any later version.
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<span class="lineNum"> 8 </span> : *
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<span class="lineNum"> 9 </span> : * This program is distributed in the hope that it will be useful,
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<span class="lineNum"> 10 </span> : * but WITHOUT ANY WARRANTY; without even the implied warranty of
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<span class="lineNum"> 11 </span> : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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<span class="lineNum"> 12 </span> : * GNU General Public License for more details.
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<span class="lineNum"> 13 </span> : */
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<span class="lineNum"> 14 </span> :
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<span class="lineNum"> 15 </span> : #ifndef __RAID_CPU_H
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<span class="lineNum"> 16 </span> : #define __RAID_CPU_H
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<span class="lineNum"> 17 </span> :
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<a name="18"><span class="lineNum"> 18 </span> : #ifdef CONFIG_X86</a>
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<span class="lineNum"> 19 </span> :
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<span class="lineNum"> 20 </span><span class="lineCov"> 2093 : static inline void raid_cpuid(uint32_t func_eax, uint32_t sub_ecx, uint32_t *reg)</span>
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<span class="lineNum"> 21 </span> : {
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<span class="lineNum"> 22 </span><span class="lineCov"> 2093 : asm volatile (</span>
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<span class="lineNum"> 23 </span> : #if defined(__i386__) && defined(__PIC__)
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<span class="lineNum"> 24 </span> : /* allow compilation in PIC mode saving ebx */
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<span class="lineNum"> 25 </span> : "xchgl %%ebx, %1\n"
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<span class="lineNum"> 26 </span> : "cpuid\n"
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<span class="lineNum"> 27 </span> : "xchgl %%ebx, %1\n"
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<span class="lineNum"> 28 </span> : : "=a" (reg[0]), "=r" (reg[1]), "=c" (reg[2]), "=d" (reg[3])
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<span class="lineNum"> 29 </span> : : "0" (func_eax), "2" (sub_ecx)
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<span class="lineNum"> 30 </span> : #else
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<span class="lineNum"> 31 </span> : "cpuid\n"
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<span class="lineNum"> 32 </span><span class="lineCov"> 2093 : : "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3])</span>
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<span class="lineNum"> 33 </span> : : "0" (func_eax), "2" (sub_ecx)
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<span class="lineNum"> 34 </span> : #endif
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<span class="lineNum"> 35 </span> : );
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<a name="36"><span class="lineNum"> 36 </span><span class="lineCov"> 2093 : }</span></a>
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<span class="lineNum"> 37 </span> :
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<span class="lineNum"> 38 </span><span class="lineCov"> 23 : static inline void raid_xgetbv(uint32_t* reg)</span>
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<span class="lineNum"> 39 </span> : {
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<span class="lineNum"> 40 </span> : /* get the value of the Extended Control Register ecx=0 */
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<span class="lineNum"> 41 </span><span class="lineCov"> 23 : asm volatile (</span>
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<span class="lineNum"> 42 </span> : /* uses a direct encoding of the XGETBV instruction as only recent */
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<span class="lineNum"> 43 </span> : /* assemblers support it. */
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<span class="lineNum"> 44 </span> : /* the next line is equivalent at: "xgetbv\n" */
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<span class="lineNum"> 45 </span> : ".byte 0x0f, 0x01, 0xd0\n"
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<span class="lineNum"> 46 </span><span class="lineCov"> 23 : : "=a" (reg[0]), "=d" (reg[3])</span>
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<span class="lineNum"> 47 </span> : : "c" (0)
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<span class="lineNum"> 48 </span> : );
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<span class="lineNum"> 49 </span><span class="lineCov"> 23 : }</span>
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<span class="lineNum"> 50 </span> :
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<a name="51"><span class="lineNum"> 51 </span> : #define CPU_VENDOR_MAX 13</a>
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<span class="lineNum"> 52 </span> :
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<span class="lineNum"> 53 </span><span class="lineCov"> 279 : static inline void raid_cpu_info(char *vendor, unsigned *family, unsigned *model)</span>
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<span class="lineNum"> 54 </span> : {
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<span class="lineNum"> 55 </span> : uint32_t reg[4];
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<span class="lineNum"> 56 </span> : unsigned f, ef, m, em;
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<span class="lineNum"> 57 </span> :
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<span class="lineNum"> 58 </span><span class="lineCov"> 279 : raid_cpuid(0, 0, reg);</span>
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<span class="lineNum"> 59 </span> :
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<span class="lineNum"> 60 </span><span class="lineCov"> 279 : ((uint32_t*)vendor)[0] = reg[1];</span>
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<span class="lineNum"> 61 </span><span class="lineCov"> 279 : ((uint32_t*)vendor)[1] = reg[3];</span>
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<span class="lineNum"> 62 </span><span class="lineCov"> 279 : ((uint32_t*)vendor)[2] = reg[2];</span>
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<span class="lineNum"> 63 </span><span class="lineCov"> 279 : vendor[12] = 0;</span>
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<span class="lineNum"> 64 </span> :
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<span class="lineNum"> 65 </span><span class="lineCov"> 279 : raid_cpuid(1, 0, reg);</span>
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<span class="lineNum"> 66 </span> :
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<span class="lineNum"> 67 </span><span class="lineCov"> 279 : f = (reg[0] >> 8) & 0xF;</span>
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<span class="lineNum"> 68 </span><span class="lineCov"> 279 : ef = (reg[0] >> 20) & 0xFF;</span>
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<span class="lineNum"> 69 </span><span class="lineCov"> 279 : m = (reg[0] >> 4) & 0xF;</span>
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<span class="lineNum"> 70 </span><span class="lineCov"> 279 : em = (reg[0] >> 16) & 0xF;</span>
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<span class="lineNum"> 71 </span> :
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<span class="lineNum"> 72 </span><span class="lineCov"> 279 : if (strcmp(vendor, "AuthenticAMD") == 0) {</span>
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<span class="lineNum"> 73 </span><span class="lineNoCov"> 0 : if (f < 15) {</span>
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<span class="lineNum"> 74 </span><span class="lineNoCov"> 0 : *family = f;</span>
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<span class="lineNum"> 75 </span><span class="lineNoCov"> 0 : *model = m;</span>
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<span class="lineNum"> 76 </span> : } else {
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<span class="lineNum"> 77 </span><span class="lineNoCov"> 0 : *family = f + ef;</span>
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<span class="lineNum"> 78 </span><span class="lineNoCov"> 0 : *model = m + (em << 4);</span>
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<span class="lineNum"> 79 </span> : }
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<span class="lineNum"> 80 </span> : } else {
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<span class="lineNum"> 81 </span><span class="lineCov"> 279 : *family = f + ef;</span>
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<span class="lineNum"> 82 </span><span class="lineCov"> 279 : *model = m + (em << 4);</span>
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<span class="lineNum"> 83 </span> : }
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<a name="84"><span class="lineNum"> 84 </span><span class="lineCov"> 279 : }</span></a>
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<span class="lineNum"> 85 </span> :
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<span class="lineNum"> 86 </span><span class="lineCov"> 1193 : static inline int raid_cpu_match_sse(uint32_t cpuid_1_ecx, uint32_t cpuid_1_edx)</span>
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<span class="lineNum"> 87 </span> : {
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<span class="lineNum"> 88 </span> : uint32_t reg[4];
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<span class="lineNum"> 89 </span> :
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<span class="lineNum"> 90 </span><span class="lineCov"> 1193 : raid_cpuid(1, 0, reg);</span>
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<span class="lineNum"> 91 </span><span class="lineCov"> 1193 : if ((reg[2] & cpuid_1_ecx) != cpuid_1_ecx)</span>
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<span class="lineNum"> 92 </span><span class="lineCov"> 18 : return 0;</span>
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<span class="lineNum"> 93 </span><span class="lineCov"> 1175 : if ((reg[3] & cpuid_1_edx) != cpuid_1_edx)</span>
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<span class="lineNum"> 94 </span><span class="lineNoCov"> 0 : return 0;</span>
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<span class="lineNum"> 95 </span> :
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<span class="lineNum"> 96 </span><span class="lineCov"> 1175 : return 1;</span>
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<a name="97"><span class="lineNum"> 97 </span> : }</a>
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<span class="lineNum"> 98 </span> :
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<span class="lineNum"> 99 </span><span class="lineCov"> 319 : static inline int raid_cpu_match_avx(uint32_t cpuid_1_ecx, uint32_t cpuid_7_ebx, uint32_t xcr0)</span>
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<span class="lineNum"> 100 </span> : {
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<span class="lineNum"> 101 </span> : uint32_t reg[4];
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<span class="lineNum"> 102 </span> :
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<span class="lineNum"> 103 </span><span class="lineCov"> 319 : raid_cpuid(1, 0, reg);</span>
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<span class="lineNum"> 104 </span><span class="lineCov"> 319 : if ((reg[2] & cpuid_1_ecx) != cpuid_1_ecx)</span>
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<span class="lineNum"> 105 </span><span class="lineCov"> 296 : return 0;</span>
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<span class="lineNum"> 106 </span> :
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<span class="lineNum"> 107 </span><span class="lineCov"> 23 : raid_xgetbv(reg);</span>
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<span class="lineNum"> 108 </span><span class="lineCov"> 23 : if ((reg[0] & xcr0) != xcr0)</span>
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<span class="lineNum"> 109 </span><span class="lineNoCov"> 0 : return 0;</span>
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<span class="lineNum"> 110 </span> :
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<span class="lineNum"> 111 </span><span class="lineCov"> 23 : raid_cpuid(7, 0, reg);</span>
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<span class="lineNum"> 112 </span><span class="lineCov"> 23 : if ((reg[1] & cpuid_7_ebx) != cpuid_7_ebx)</span>
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<span class="lineNum"> 113 </span><span class="lineNoCov"> 0 : return 0;</span>
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<span class="lineNum"> 114 </span> :
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<span class="lineNum"> 115 </span><span class="lineCov"> 23 : return 1;</span>
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<a name="116"><span class="lineNum"> 116 </span> : }</a>
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<span class="lineNum"> 117 </span> :
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<span class="lineNum"> 118 </span><span class="lineCov"> 307 : static inline int raid_cpu_has_sse2(void)</span>
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<span class="lineNum"> 119 </span> : {
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<span class="lineNum"> 120 </span> : /*
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<span class="lineNum"> 121 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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<span class="lineNum"> 122 </span> : * 325462-048US September 2013
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<span class="lineNum"> 123 </span> : *
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<span class="lineNum"> 124 </span> : * 11.6.2 Checking for SSE/SSE2 Support
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<span class="lineNum"> 125 </span> : * Before an application attempts to use the SSE and/or SSE2 extensions, it should check
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<span class="lineNum"> 126 </span> : * that they are present on the processor:
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<span class="lineNum"> 127 </span> : * 1. Check that the processor supports the CPUID instruction. Bit 21 of the EFLAGS
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<span class="lineNum"> 128 </span> : * register can be used to check processor's support the CPUID instruction.
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<span class="lineNum"> 129 </span> : * 2. Check that the processor supports the SSE and/or SSE2 extensions (true if
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<span class="lineNum"> 130 </span> : * CPUID.01H:EDX.SSE[bit 25] = 1 and/or CPUID.01H:EDX.SSE2[bit 26] = 1).
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<span class="lineNum"> 131 </span> : */
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<span class="lineNum"> 132 </span><span class="lineCov"> 307 : return raid_cpu_match_sse(</span>
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<span class="lineNum"> 133 </span> : 0,
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<span class="lineNum"> 134 </span> : 1 << 26); /* SSE2 */
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<a name="135"><span class="lineNum"> 135 </span> : }</a>
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<span class="lineNum"> 136 </span> :
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<span class="lineNum"> 137 </span><span class="lineCov"> 591 : static inline int raid_cpu_has_ssse3(void)</span>
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<span class="lineNum"> 138 </span> : {
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<span class="lineNum"> 139 </span> : /*
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<span class="lineNum"> 140 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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<span class="lineNum"> 141 </span> : * 325462-048US September 2013
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<span class="lineNum"> 142 </span> : *
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<span class="lineNum"> 143 </span> : * 12.7.2 Checking for SSSE3 Support
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<span class="lineNum"> 144 </span> : * Before an application attempts to use the SSSE3 extensions, the application should
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<span class="lineNum"> 145 </span> : * follow the steps illustrated in Section 11.6.2, "Checking for SSE/SSE2 Support."
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<span class="lineNum"> 146 </span> : * Next, use the additional step provided below:
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<span class="lineNum"> 147 </span> : * Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
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<span class="lineNum"> 148 </span> : */
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<span class="lineNum"> 149 </span><span class="lineCov"> 591 : return raid_cpu_match_sse(</span>
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<span class="lineNum"> 150 </span> : 1 << 9, /* SSSE3 */
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<span class="lineNum"> 151 </span> : 1 << 26); /* SSE2 */
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<a name="152"><span class="lineNum"> 152 </span> : }</a>
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<span class="lineNum"> 153 </span> :
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<span class="lineNum"> 154 </span><span class="lineCov"> 295 : static inline int raid_cpu_has_crc32(void)</span>
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<span class="lineNum"> 155 </span> : {
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<span class="lineNum"> 156 </span> : /*
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<span class="lineNum"> 157 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual
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<span class="lineNum"> 158 </span> : * 325462-048US September 2013
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<span class="lineNum"> 159 </span> : *
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<span class="lineNum"> 160 </span> : * 12.12.3 Checking for SSE4.2 Support
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<span class="lineNum"> 161 </span> : * ...
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<span class="lineNum"> 162 </span> : * Before an application attempts to use the CRC32 instruction, it must check
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<span class="lineNum"> 163 </span> : * that the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1).
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<span class="lineNum"> 164 </span> : */
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<span class="lineNum"> 165 </span><span class="lineCov"> 295 : return raid_cpu_match_sse(</span>
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<span class="lineNum"> 166 </span> : 1 << 20, /* CRC32 */
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<span class="lineNum"> 167 </span> : 0);
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<a name="168"><span class="lineNum"> 168 </span> : }</a>
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<span class="lineNum"> 169 </span> :
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<span class="lineNum"> 170 </span><span class="lineCov"> 319 : static inline int raid_cpu_has_avx2(void)</span>
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<span class="lineNum"> 171 </span> : {
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<span class="lineNum"> 172 </span> : /*
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<span class="lineNum"> 173 </span> : * Intel Architecture Instruction Set Extensions Programming Reference
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<span class="lineNum"> 174 </span> : * 319433-022 October 2014
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<span class="lineNum"> 175 </span> : *
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<span class="lineNum"> 176 </span> : * 14.3 Detection of AVX instructions
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<span class="lineNum"> 177 </span> : * 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)
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<span class="lineNum"> 178 </span> : * 2) Issue XGETBV and verify that XCR0[2:1] = `11b' (XMM state and YMM state are enabled by OS).
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<span class="lineNum"> 179 </span> : * 3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
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<span class="lineNum"> 180 </span> : * (Step 3 can be done in any order relative to 1 and 2)
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<span class="lineNum"> 181 </span> : *
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<span class="lineNum"> 182 </span> : * 14.7.1 Detection of AVX2
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<span class="lineNum"> 183 </span> : * Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.
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<span class="lineNum"> 184 </span> : * Application Software must identify that hardware supports AVX, after that it must
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<span class="lineNum"> 185 </span> : * also detect support for AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5].
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<span class="lineNum"> 186 </span> : */
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<span class="lineNum"> 187 </span><span class="lineCov"> 319 : return raid_cpu_match_avx(</span>
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<span class="lineNum"> 188 </span> : (1 << 27) | (1 << 28), /* OSXSAVE and AVX */
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<span class="lineNum"> 189 </span> : 1 << 5, /* AVX2 */
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<span class="lineNum"> 190 </span> : 3 << 1); /* OS saves XMM and YMM registers */
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<span class="lineNum"> 191 </span> : }
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<span class="lineNum"> 192 </span> :
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<span class="lineNum"> 193 </span> : static inline int raid_cpu_has_avx512bw(void)
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<span class="lineNum"> 194 </span> : {
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<span class="lineNum"> 195 </span> : /*
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<span class="lineNum"> 196 </span> : * Intel Architecture Instruction Set Extensions Programming Reference
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<span class="lineNum"> 197 </span> : * 319433-022 October 2014
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<span class="lineNum"> 198 </span> : *
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<span class="lineNum"> 199 </span> : * 2.2 Detection of 512-bit Instruction Groups of Intel AVX-512 Family
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<span class="lineNum"> 200 </span> : * 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use)
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<span class="lineNum"> 201 </span> : * 2) Execute XGETBV and verify that XCR0[7:5] = `111b' (OPMASK state, upper 256-bit of
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<span class="lineNum"> 202 </span> : * ZMM0-ZMM15 and ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = `11b'
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<span class="lineNum"> 203 </span> : * (XMM state and YMM state are enabled by OS).
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<span class="lineNum"> 204 </span> : * 3) Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512BW[bit 30] = 1.
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<span class="lineNum"> 205 </span> : */
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<span class="lineNum"> 206 </span> :
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<span class="lineNum"> 207 </span> : /* note that intentionally we don't check for AVX and AVX2 */
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||
<span class="lineNum"> 208 </span> : /* because the documentation doesn't require that */
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<span class="lineNum"> 209 </span> : return raid_cpu_match_avx(
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<span class="lineNum"> 210 </span> : 1 << 27, /* XSAVE/XGETBV */
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<span class="lineNum"> 211 </span> : (1 << 16) | (1 << 30), /* AVX512F and AVX512BW */
|
||
<span class="lineNum"> 212 </span> : (3 << 1) | (7 << 5)); /* OS saves XMM, YMM and ZMM registers */
|
||
<span class="lineNum"> 213 </span> : }
|
||
<span class="lineNum"> 214 </span> :
|
||
<span class="lineNum"> 215 </span> : /**
|
||
<a name="216"><span class="lineNum"> 216 </span> : * Check if it's an Intel Atom CPU.</a>
|
||
<span class="lineNum"> 217 </span> : */
|
||
<span class="lineNum"> 218 </span><span class="lineCov"> 275 : static inline int raid_cpu_is_atom(unsigned family, unsigned model)</span>
|
||
<span class="lineNum"> 219 </span> : {
|
||
<span class="lineNum"> 220 </span><span class="lineCov"> 275 : if (family != 6)</span>
|
||
<span class="lineNum"> 221 </span><span class="lineCov"> 3 : return 0;</span>
|
||
<span class="lineNum"> 222 </span> :
|
||
<span class="lineNum"> 223 </span> : /*
|
||
<span class="lineNum"> 224 </span> : * x86 Architecture CPUID
|
||
<span class="lineNum"> 225 </span> : * http://www.sandpile.org/x86/cpuid.htm
|
||
<span class="lineNum"> 226 </span> : *
|
||
<span class="lineNum"> 227 </span> : * Intel Atom
|
||
<span class="lineNum"> 228 </span> : * 1C (28) Atom (45 nm) with 512 KB on-die L2
|
||
<span class="lineNum"> 229 </span> : * 26 (38) Atom (45 nm) with 512 KB on-die L2
|
||
<span class="lineNum"> 230 </span> : * 36 (54) Atom (32 nm) with 512 KB on-die L2
|
||
<span class="lineNum"> 231 </span> : * 27 (39) Atom (32 nm) with 512 KB on-die L2
|
||
<span class="lineNum"> 232 </span> : * 35 (53) Atom (?? nm) with ??? KB on-die L2
|
||
<span class="lineNum"> 233 </span> : * 4A (74) Atom 2C (22 nm) 1 MB L2 + PowerVR (TGR)
|
||
<span class="lineNum"> 234 </span> : * 5A (90) Atom 4C (22 nm) 2 MB L2 + PowerVR (ANN)
|
||
<span class="lineNum"> 235 </span> : * 37 (55) Atom 4C (22 nm) 2 MB L2 + Intel Gen7 (BYT)
|
||
<span class="lineNum"> 236 </span> : * 4C (76) Atom 4C (14 nm) 2 MB L2 + Intel Gen8 (BSW)
|
||
<span class="lineNum"> 237 </span> : * 5D (93) Atom 4C (28 nm TSMC) 1 MB L2 + Mali (SoFIA)
|
||
<span class="lineNum"> 238 </span> : * 4D (77) Atom 8C (22 nm) 4 MB L2 (AVN)
|
||
<span class="lineNum"> 239 </span> : * ?? Atom ?C (14 nm) ? MB L2 (DVN)
|
||
<span class="lineNum"> 240 </span> : */
|
||
<span class="lineNum"> 241 </span><span class="lineCov"> 544 : return model == 28 || model == 38 || model == 54</span>
|
||
<span class="lineNum"> 242 </span><span class="lineCov"> 272 : || model == 39 || model == 53 || model == 74</span>
|
||
<span class="lineNum"> 243 </span><span class="lineCov"> 272 : || model == 90 || model == 55 || model == 76</span>
|
||
<span class="lineNum"> 244 </span><span class="lineCov"> 544 : || model == 93 || model == 77;</span>
|
||
<span class="lineNum"> 245 </span> : }
|
||
<span class="lineNum"> 246 </span> :
|
||
<span class="lineNum"> 247 </span> : /**
|
||
<span class="lineNum"> 248 </span> : * Check if the processor has a slow MULT implementation.
|
||
<a name="249"><span class="lineNum"> 249 </span> : * If yes, it's better to use a hash not based on multiplication.</a>
|
||
<span class="lineNum"> 250 </span> : */
|
||
<span class="lineNum"> 251 </span><span class="lineCov"> 271 : static inline int raid_cpu_has_slowmult(void)</span>
|
||
<span class="lineNum"> 252 </span> : {
|
||
<span class="lineNum"> 253 </span> : char vendor[CPU_VENDOR_MAX];
|
||
<span class="lineNum"> 254 </span> : unsigned family;
|
||
<span class="lineNum"> 255 </span> : unsigned model;
|
||
<span class="lineNum"> 256 </span> :
|
||
<span class="lineNum"> 257 </span> : /*
|
||
<span class="lineNum"> 258 </span> : * In some cases Murmur3 based on MUL instruction,
|
||
<span class="lineNum"> 259 </span> : * is a LOT slower than Spooky2 based on SHIFTs.
|
||
<span class="lineNum"> 260 </span> : */
|
||
<span class="lineNum"> 261 </span><span class="lineCov"> 271 : raid_cpu_info(vendor, &family, &model);</span>
|
||
<span class="lineNum"> 262 </span> :
|
||
<span class="lineNum"> 263 </span><span class="lineCov"> 271 : if (strcmp(vendor, "GenuineIntel") == 0) {</span>
|
||
<span class="lineNum"> 264 </span> : /*
|
||
<span class="lineNum"> 265 </span> : * Intel Atom (Model 28)
|
||
<span class="lineNum"> 266 </span> : * murmur3:378 MB/s, spooky2:3413 MB/s (x86)
|
||
<span class="lineNum"> 267 </span> : *
|
||
<span class="lineNum"> 268 </span> : * Intel Atom (Model 77)
|
||
<span class="lineNum"> 269 </span> : * murmur3:1311 MB/s, spooky2:4056 MB/s (x64)
|
||
<span class="lineNum"> 270 </span> : */
|
||
<span class="lineNum"> 271 </span><span class="lineCov"> 271 : if (raid_cpu_is_atom(family, model))</span>
|
||
<span class="lineNum"> 272 </span><span class="lineNoCov"> 0 : return 1;</span>
|
||
<span class="lineNum"> 273 </span> : }
|
||
<span class="lineNum"> 274 </span> :
|
||
<span class="lineNum"> 275 </span><span class="lineCov"> 271 : return 0;</span>
|
||
<span class="lineNum"> 276 </span> : }
|
||
<span class="lineNum"> 277 </span> :
|
||
<span class="lineNum"> 278 </span> : /**
|
||
<span class="lineNum"> 279 </span> : * Check if the processor has a slow extended set of SSE registers.
|
||
<a name="280"><span class="lineNum"> 280 </span> : * If yes, it's better to limit the unroll to the firsrt 8 registers.</a>
|
||
<span class="lineNum"> 281 </span> : */
|
||
<span class="lineNum"> 282 </span><span class="lineCov"> 4 : static inline int raid_cpu_has_slowextendedreg(void)</span>
|
||
<span class="lineNum"> 283 </span> : {
|
||
<span class="lineNum"> 284 </span> : char vendor[CPU_VENDOR_MAX];
|
||
<span class="lineNum"> 285 </span> : unsigned family;
|
||
<span class="lineNum"> 286 </span> : unsigned model;
|
||
<span class="lineNum"> 287 </span> :
|
||
<span class="lineNum"> 288 </span> : /*
|
||
<span class="lineNum"> 289 </span> : * In some cases the PAR2 implementation using 16 SSE registers
|
||
<span class="lineNum"> 290 </span> : * is a LITTLE slower than the one using only the first 8 registers.
|
||
<span class="lineNum"> 291 </span> : * This doesn't happen for PARZ.
|
||
<span class="lineNum"> 292 </span> : */
|
||
<span class="lineNum"> 293 </span><span class="lineCov"> 4 : raid_cpu_info(vendor, &family, &model);</span>
|
||
<span class="lineNum"> 294 </span> :
|
||
<span class="lineNum"> 295 </span><span class="lineCov"> 4 : if (strcmp(vendor, "AuthenticAMD") == 0) {</span>
|
||
<span class="lineNum"> 296 </span> : /*
|
||
<span class="lineNum"> 297 </span> : * AMD Bulldozer
|
||
<span class="lineNum"> 298 </span> : * par2_sse2:4922 MB/s, par2_sse2e:4465 MB/s
|
||
<span class="lineNum"> 299 </span> : */
|
||
<span class="lineNum"> 300 </span><span class="lineNoCov"> 0 : if (family == 21)</span>
|
||
<span class="lineNum"> 301 </span><span class="lineNoCov"> 0 : return 1;</span>
|
||
<span class="lineNum"> 302 </span> : }
|
||
<span class="lineNum"> 303 </span> :
|
||
<span class="lineNum"> 304 </span><span class="lineCov"> 4 : if (strcmp(vendor, "GenuineIntel") == 0) {</span>
|
||
<span class="lineNum"> 305 </span> : /*
|
||
<span class="lineNum"> 306 </span> : * Intel Atom (Model 77)
|
||
<span class="lineNum"> 307 </span> : * par2_sse2:5686 MB/s, par2_sse2e:5250 MB/s
|
||
<span class="lineNum"> 308 </span> : * parz_sse2:3100 MB/s, parz_sse2e:3400 MB/s
|
||
<span class="lineNum"> 309 </span> : * par3_sse3:1921 MB/s, par3_sse3e:1813 MB/s
|
||
<span class="lineNum"> 310 </span> : * par4_sse3:1175 MB/s, par4_sse3e:1113 MB/s
|
||
<span class="lineNum"> 311 </span> : * par5_sse3:876 MB/s, par5_sse3e:675 MB/s
|
||
<span class="lineNum"> 312 </span> : * par6_sse3:705 MB/s, par6_sse3e:529 MB/s
|
||
<span class="lineNum"> 313 </span> : *
|
||
<span class="lineNum"> 314 </span> : * Intel Atom (Model 77) "Avoton C2750"
|
||
<span class="lineNum"> 315 </span> : * par2_sse2:5661 MB/s, par2_sse2e:5382 MB/s
|
||
<span class="lineNum"> 316 </span> : * parz_sse2:3110 MB/s, parz_sse2e:3450 MB/s
|
||
<span class="lineNum"> 317 </span> : * par3_sse3:1769 MB/s, par3_sse3e:1856 MB/s
|
||
<span class="lineNum"> 318 </span> : * par4_sse3:1221 MB/s, par4_sse3e:1141 MB/s
|
||
<span class="lineNum"> 319 </span> : * par5_sse3:910 MB/s, par5_sse3e:675 MB/s
|
||
<span class="lineNum"> 320 </span> : * par6_sse3:720 MB/s, par6_sse3e:534 MB/s
|
||
<span class="lineNum"> 321 </span> : */
|
||
<span class="lineNum"> 322 </span><span class="lineCov"> 4 : if (raid_cpu_is_atom(family, model))</span>
|
||
<span class="lineNum"> 323 </span><span class="lineNoCov"> 0 : return 1;</span>
|
||
<span class="lineNum"> 324 </span> : }
|
||
<span class="lineNum"> 325 </span> :
|
||
<span class="lineNum"> 326 </span><span class="lineCov"> 4 : return 0;</span>
|
||
<span class="lineNum"> 327 </span> : }
|
||
<span class="lineNum"> 328 </span> : #endif
|
||
<span class="lineNum"> 329 </span> :
|
||
<span class="lineNum"> 330 </span> : #endif
|
||
<span class="lineNum"> 331 </span> :
|
||
</pre>
|
||
</td>
|
||
</tr>
|
||
</table>
|
||
<br>
|
||
|
||
<table width="100%" border=0 cellspacing=0 cellpadding=0>
|
||
<tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
|
||
<tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.10</a></td></tr>
|
||
</table>
|
||
<br>
|
||
|
||
</body>
|
||
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