snapraid/cov/raid/internal.h.gcov.html
Andrea Mazzoleni e01ca1e0fa Auto update
2016-11-21 19:48:21 +01:00

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<td class="headerCovTableEntry">5</td>
<td class="headerCovTableEntry">5</td>
<td class="headerCovTableEntryHi">100.0 %</td>
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<td class="headerValue">2016-11-21</td>
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<pre class="sourceHeading"> Line data Source code</pre>
<pre class="source">
<a name="1"><span class="lineNum"> 1 </span> : /*</a>
<span class="lineNum"> 2 </span> : * Copyright (C) 2013 Andrea Mazzoleni
<span class="lineNum"> 3 </span> : *
<span class="lineNum"> 4 </span> : * This program is free software: you can redistribute it and/or modify
<span class="lineNum"> 5 </span> : * it under the terms of the GNU General Public License as published by
<span class="lineNum"> 6 </span> : * the Free Software Foundation, either version 2 of the License, or
<span class="lineNum"> 7 </span> : * (at your option) any later version.
<span class="lineNum"> 8 </span> : *
<span class="lineNum"> 9 </span> : * This program is distributed in the hope that it will be useful,
<span class="lineNum"> 10 </span> : * but WITHOUT ANY WARRANTY; without even the implied warranty of
<span class="lineNum"> 11 </span> : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
<span class="lineNum"> 12 </span> : * GNU General Public License for more details.
<span class="lineNum"> 13 </span> : */
<span class="lineNum"> 14 </span> :
<span class="lineNum"> 15 </span> : #ifndef __RAID_INTERNAL_H
<span class="lineNum"> 16 </span> : #define __RAID_INTERNAL_H
<span class="lineNum"> 17 </span> :
<span class="lineNum"> 18 </span> : /*
<span class="lineNum"> 19 </span> : * Supported instruction sets.
<span class="lineNum"> 20 </span> : *
<span class="lineNum"> 21 </span> : * It may happen that the assembler is too old to support
<span class="lineNum"> 22 </span> : * all instructions, even if the architecture supports them.
<span class="lineNum"> 23 </span> : * These defines allow to exclude from the build the not supported ones.
<span class="lineNum"> 24 </span> : *
<span class="lineNum"> 25 </span> : * If in your project you use a predefined assembler, you can define them
<span class="lineNum"> 26 </span> : * using fixed values, instead of using the HAVE_* defines.
<span class="lineNum"> 27 </span> : */
<span class="lineNum"> 28 </span> : #if HAVE_CONFIG_H
<span class="lineNum"> 29 </span> :
<span class="lineNum"> 30 </span> : /* Includes the project configuration for HAVE_* defines */
<span class="lineNum"> 31 </span> : #include &quot;config.h&quot;
<span class="lineNum"> 32 </span> :
<span class="lineNum"> 33 </span> : /* If the compiler supports assembly */
<span class="lineNum"> 34 </span> : #if HAVE_ASSEMBLY
<span class="lineNum"> 35 </span> : /* Autodetect from the compiler */
<span class="lineNum"> 36 </span> : #if defined(__i386__)
<span class="lineNum"> 37 </span> : #define CONFIG_X86 1
<span class="lineNum"> 38 </span> : #define CONFIG_X86_32 1
<span class="lineNum"> 39 </span> : #endif
<span class="lineNum"> 40 </span> : #if defined(__x86_64__)
<span class="lineNum"> 41 </span> : #define CONFIG_X86 1
<span class="lineNum"> 42 </span> : #define CONFIG_X86_64 1
<span class="lineNum"> 43 </span> : #endif
<span class="lineNum"> 44 </span> : #endif
<span class="lineNum"> 45 </span> :
<span class="lineNum"> 46 </span> : /* Enables SSE2, SSSE3, AVX2 only if the assembler supports it */
<span class="lineNum"> 47 </span> : #if HAVE_SSE2
<span class="lineNum"> 48 </span> : #define CONFIG_SSE2 1
<span class="lineNum"> 49 </span> : #endif
<span class="lineNum"> 50 </span> : #if HAVE_SSSE3
<span class="lineNum"> 51 </span> : #define CONFIG_SSSE3 1
<span class="lineNum"> 52 </span> : #endif
<span class="lineNum"> 53 </span> : #if HAVE_AVX2
<span class="lineNum"> 54 </span> : #define CONFIG_AVX2 1
<span class="lineNum"> 55 </span> : #endif
<span class="lineNum"> 56 </span> :
<span class="lineNum"> 57 </span> : #else /* if HAVE_CONFIG_H is not defined */
<span class="lineNum"> 58 </span> :
<span class="lineNum"> 59 </span> : /* Assume that assembly is always supported */
<span class="lineNum"> 60 </span> : #if defined(__i386__)
<span class="lineNum"> 61 </span> : #define CONFIG_X86 1
<span class="lineNum"> 62 </span> : #define CONFIG_X86_32 1
<span class="lineNum"> 63 </span> : #endif
<span class="lineNum"> 64 </span> :
<span class="lineNum"> 65 </span> : #if defined(__x86_64__)
<span class="lineNum"> 66 </span> : #define CONFIG_X86 1
<span class="lineNum"> 67 </span> : #define CONFIG_X86_64 1
<span class="lineNum"> 68 </span> : #endif
<span class="lineNum"> 69 </span> :
<span class="lineNum"> 70 </span> : /* Assumes that the assembler supports everything */
<span class="lineNum"> 71 </span> : #ifdef CONFIG_X86
<span class="lineNum"> 72 </span> : #define CONFIG_SSE2 1
<span class="lineNum"> 73 </span> : #define CONFIG_SSSE3 1
<span class="lineNum"> 74 </span> : #define CONFIG_AVX2 1
<span class="lineNum"> 75 </span> : #endif
<span class="lineNum"> 76 </span> : #endif
<span class="lineNum"> 77 </span> :
<span class="lineNum"> 78 </span> : /*
<span class="lineNum"> 79 </span> : * Includes anything required for compatibility.
<span class="lineNum"> 80 </span> : */
<span class="lineNum"> 81 </span> : #include &lt;assert.h&gt;
<span class="lineNum"> 82 </span> : #include &lt;stdint.h&gt;
<span class="lineNum"> 83 </span> : #include &lt;stdlib.h&gt;
<span class="lineNum"> 84 </span> : #include &lt;string.h&gt;
<span class="lineNum"> 85 </span> :
<span class="lineNum"> 86 </span> : /*
<span class="lineNum"> 87 </span> : * Inverse assert.
<span class="lineNum"> 88 </span> : */
<span class="lineNum"> 89 </span> : #define BUG_ON(a) assert(!(a))
<span class="lineNum"> 90 </span> :
<span class="lineNum"> 91 </span> : /*
<span class="lineNum"> 92 </span> : * Forced inline.
<span class="lineNum"> 93 </span> : */
<span class="lineNum"> 94 </span> : #ifndef __always_inline
<span class="lineNum"> 95 </span> : #define __always_inline inline __attribute__((always_inline))
<span class="lineNum"> 96 </span> : #endif
<span class="lineNum"> 97 </span> :
<span class="lineNum"> 98 </span> : /*
<span class="lineNum"> 99 </span> : * Forced alignment.
<span class="lineNum"> 100 </span> : */
<span class="lineNum"> 101 </span> : #ifndef __aligned
<span class="lineNum"> 102 </span> : #define __aligned(a) __attribute__((aligned(a)))
<span class="lineNum"> 103 </span> : #endif
<span class="lineNum"> 104 </span> :
<span class="lineNum"> 105 </span> : /*
<span class="lineNum"> 106 </span> : * Align a pointer at the specified size.
<span class="lineNum"> 107 </span> : */
<span class="lineNum"> 108 </span> : static __always_inline void *__align_ptr(void *ptr, uintptr_t size)
<span class="lineNum"> 109 </span> : {
<span class="lineNum"> 110 </span><span class="lineCov"> 711884 : uintptr_t offset = (uintptr_t)ptr;</span>
<span class="lineNum"> 111 </span> :
<span class="lineNum"> 112 </span><span class="lineCov"> 711884 : offset = (offset + size - 1U) &amp; ~(size - 1U);</span>
<span class="lineNum"> 113 </span> :
<span class="lineNum"> 114 </span><span class="lineCov"> 711884 : return (void *)offset;</span>
<span class="lineNum"> 115 </span> : }
<span class="lineNum"> 116 </span> :
<span class="lineNum"> 117 </span> : /*
<span class="lineNum"> 118 </span> : * Includes the main interface headers.
<span class="lineNum"> 119 </span> : */
<span class="lineNum"> 120 </span> : #include &quot;raid.h&quot;
<span class="lineNum"> 121 </span> : #include &quot;helper.h&quot;
<span class="lineNum"> 122 </span> :
<span class="lineNum"> 123 </span> : /*
<span class="lineNum"> 124 </span> : * Internal functions.
<span class="lineNum"> 125 </span> : *
<span class="lineNum"> 126 </span> : * These are intended to provide access for testing.
<span class="lineNum"> 127 </span> : */
<span class="lineNum"> 128 </span> : int raid_selftest(void);
<span class="lineNum"> 129 </span> : void raid_gen_ref(int nd, int np, size_t size, void **vv);
<span class="lineNum"> 130 </span> : void raid_invert(uint8_t *M, uint8_t *V, int n);
<span class="lineNum"> 131 </span> : void raid_delta_gen(int nr, int *id, int *ip, int nd, size_t size, void **v);
<span class="lineNum"> 132 </span> : void raid_rec1of1(int *id, int nd, size_t size, void **v);
<span class="lineNum"> 133 </span> : void raid_rec2of2_int8(int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 134 </span> : void raid_gen1_int32(int nd, size_t size, void **vv);
<span class="lineNum"> 135 </span> : void raid_gen1_int64(int nd, size_t size, void **vv);
<span class="lineNum"> 136 </span> : void raid_gen1_sse2(int nd, size_t size, void **vv);
<span class="lineNum"> 137 </span> : void raid_gen1_avx2(int nd, size_t size, void **vv);
<span class="lineNum"> 138 </span> : void raid_gen2_int32(int nd, size_t size, void **vv);
<span class="lineNum"> 139 </span> : void raid_gen2_int64(int nd, size_t size, void **vv);
<span class="lineNum"> 140 </span> : void raid_gen2_sse2(int nd, size_t size, void **vv);
<span class="lineNum"> 141 </span> : void raid_gen2_avx2(int nd, size_t size, void **vv);
<span class="lineNum"> 142 </span> : void raid_gen2_sse2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 143 </span> : void raid_genz_int32(int nd, size_t size, void **vv);
<span class="lineNum"> 144 </span> : void raid_genz_int64(int nd, size_t size, void **vv);
<span class="lineNum"> 145 </span> : void raid_genz_sse2(int nd, size_t size, void **vv);
<span class="lineNum"> 146 </span> : void raid_genz_sse2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 147 </span> : void raid_genz_avx2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 148 </span> : void raid_gen3_int8(int nd, size_t size, void **vv);
<span class="lineNum"> 149 </span> : void raid_gen3_ssse3(int nd, size_t size, void **vv);
<span class="lineNum"> 150 </span> : void raid_gen3_ssse3ext(int nd, size_t size, void **vv);
<span class="lineNum"> 151 </span> : void raid_gen3_avx2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 152 </span> : void raid_gen4_int8(int nd, size_t size, void **vv);
<span class="lineNum"> 153 </span> : void raid_gen4_ssse3(int nd, size_t size, void **vv);
<span class="lineNum"> 154 </span> : void raid_gen4_ssse3ext(int nd, size_t size, void **vv);
<span class="lineNum"> 155 </span> : void raid_gen4_avx2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 156 </span> : void raid_gen5_int8(int nd, size_t size, void **vv);
<span class="lineNum"> 157 </span> : void raid_gen5_ssse3(int nd, size_t size, void **vv);
<span class="lineNum"> 158 </span> : void raid_gen5_ssse3ext(int nd, size_t size, void **vv);
<span class="lineNum"> 159 </span> : void raid_gen5_avx2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 160 </span> : void raid_gen6_int8(int nd, size_t size, void **vv);
<span class="lineNum"> 161 </span> : void raid_gen6_ssse3(int nd, size_t size, void **vv);
<span class="lineNum"> 162 </span> : void raid_gen6_ssse3ext(int nd, size_t size, void **vv);
<span class="lineNum"> 163 </span> : void raid_gen6_avx2ext(int nd, size_t size, void **vv);
<span class="lineNum"> 164 </span> : void raid_rec1_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 165 </span> : void raid_rec2_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 166 </span> : void raid_recX_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 167 </span> : void raid_rec1_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 168 </span> : void raid_rec2_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 169 </span> : void raid_recX_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 170 </span> : void raid_rec1_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 171 </span> : void raid_rec2_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 172 </span> : void raid_recX_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 173 </span> :
<span class="lineNum"> 174 </span> : /*
<span class="lineNum"> 175 </span> : * Internal naming.
<span class="lineNum"> 176 </span> : *
<span class="lineNum"> 177 </span> : * These are intented to provide access for testing.
<span class="lineNum"> 178 </span> : */
<span class="lineNum"> 179 </span> : const char *raid_gen1_tag(void);
<span class="lineNum"> 180 </span> : const char *raid_gen2_tag(void);
<span class="lineNum"> 181 </span> : const char *raid_genz_tag(void);
<span class="lineNum"> 182 </span> : const char *raid_gen3_tag(void);
<span class="lineNum"> 183 </span> : const char *raid_gen4_tag(void);
<span class="lineNum"> 184 </span> : const char *raid_gen5_tag(void);
<span class="lineNum"> 185 </span> : const char *raid_gen6_tag(void);
<span class="lineNum"> 186 </span> : const char *raid_rec1_tag(void);
<span class="lineNum"> 187 </span> : const char *raid_rec2_tag(void);
<span class="lineNum"> 188 </span> : const char *raid_recX_tag(void);
<span class="lineNum"> 189 </span> :
<span class="lineNum"> 190 </span> : /*
<span class="lineNum"> 191 </span> : * Internal forwarders.
<span class="lineNum"> 192 </span> : */
<span class="lineNum"> 193 </span> : extern void (*raid_gen3_ptr)(int nd, size_t size, void **vv);
<span class="lineNum"> 194 </span> : extern void (*raid_genz_ptr)(int nd, size_t size, void **vv);
<span class="lineNum"> 195 </span> : extern void (*raid_gen_ptr[RAID_PARITY_MAX])(
<span class="lineNum"> 196 </span> : int nd, size_t size, void **vv);
<span class="lineNum"> 197 </span> : extern void (*raid_rec_ptr[RAID_PARITY_MAX])(
<span class="lineNum"> 198 </span> : int nr, int *id, int *ip, int nd, size_t size, void **vv);
<span class="lineNum"> 199 </span> :
<span class="lineNum"> 200 </span> : /*
<span class="lineNum"> 201 </span> : * Tables.
<span class="lineNum"> 202 </span> : */
<span class="lineNum"> 203 </span> : extern const uint8_t raid_gfmul[256][256] __aligned(256);
<span class="lineNum"> 204 </span> : extern const uint8_t raid_gfexp[256] __aligned(256);
<span class="lineNum"> 205 </span> : extern const uint8_t raid_gfinv[256] __aligned(256);
<span class="lineNum"> 206 </span> : extern const uint8_t raid_gfvandermonde[3][256] __aligned(256);
<span class="lineNum"> 207 </span> : extern const uint8_t raid_gfcauchy[6][256] __aligned(256);
<span class="lineNum"> 208 </span> : extern const uint8_t raid_gfcauchypshufb[251][4][2][16] __aligned(256);
<span class="lineNum"> 209 </span> : extern const uint8_t raid_gfmulpshufb[256][2][16] __aligned(256);
<span class="lineNum"> 210 </span> : extern const uint8_t (*raid_gfgen)[256];
<span class="lineNum"> 211 </span> : #define gfmul raid_gfmul
<span class="lineNum"> 212 </span> : #define gfexp raid_gfexp
<span class="lineNum"> 213 </span> : #define gfinv raid_gfinv
<span class="lineNum"> 214 </span> : #define gfvandermonde raid_gfvandermonde
<span class="lineNum"> 215 </span> : #define gfcauchy raid_gfcauchy
<span class="lineNum"> 216 </span> : #define gfgenpshufb raid_gfcauchypshufb
<span class="lineNum"> 217 </span> : #define gfmulpshufb raid_gfmulpshufb
<span class="lineNum"> 218 </span> : #define gfgen raid_gfgen
<span class="lineNum"> 219 </span> :
<span class="lineNum"> 220 </span> : /*
<span class="lineNum"> 221 </span> : * Assembler blocks.
<span class="lineNum"> 222 </span> : */
<span class="lineNum"> 223 </span> : #ifdef CONFIG_X86
<span class="lineNum"> 224 </span> : #ifdef CONFIG_SSE2
<span class="lineNum"> 225 </span> : static __always_inline void raid_sse_begin(void)
<span class="lineNum"> 226 </span> : {
<span class="lineNum"> 227 </span> : }
<span class="lineNum"> 228 </span> :
<span class="lineNum"> 229 </span> : static __always_inline void raid_sse_end(void)
<span class="lineNum"> 230 </span> : {
<span class="lineNum"> 231 </span> : /* SSE and AVX code uses non-temporal writes, like MOVNTDQ, */
<span class="lineNum"> 232 </span> : /* that use a weak memory model. To ensure that other processors */
<span class="lineNum"> 233 </span> : /* see correctly the data written, we use a store-store memory */
<span class="lineNum"> 234 </span> : /* barrier at the end of the asm code */
<span class="lineNum"> 235 </span><span class="lineCov"> 1388567 : asm volatile (&quot;sfence&quot; : : : &quot;memory&quot;);</span>
<span class="lineNum"> 236 </span> :
<span class="lineNum"> 237 </span> : /* clobbers registers used in the asm code */
<span class="lineNum"> 238 </span> : /* this is required because in the Windows ABI, */
<span class="lineNum"> 239 </span> : /* registers xmm6-xmm15 should be kept by the callee. */
<span class="lineNum"> 240 </span> : /* this clobber list force the compiler to save any */
<span class="lineNum"> 241 </span> : /* register that needs to be saved */
<span class="lineNum"> 242 </span> : /* we check for __SSE2_ because we require that the */
<span class="lineNum"> 243 </span> : /* compiler supports SSE2 registers in the clobber list */
<span class="lineNum"> 244 </span> : #ifdef __SSE2__
<span class="lineNum"> 245 </span> : asm volatile (&quot;&quot; : : : &quot;%xmm0&quot;, &quot;%xmm1&quot;, &quot;%xmm2&quot;, &quot;%xmm3&quot;);
<span class="lineNum"> 246 </span> : asm volatile (&quot;&quot; : : : &quot;%xmm4&quot;, &quot;%xmm5&quot;, &quot;%xmm6&quot;, &quot;%xmm7&quot;);
<span class="lineNum"> 247 </span> : #ifdef CONFIG_X86_64
<span class="lineNum"> 248 </span> : asm volatile (&quot;&quot; : : : &quot;%xmm8&quot;, &quot;%xmm9&quot;, &quot;%xmm10&quot;, &quot;%xmm11&quot;);
<span class="lineNum"> 249 </span> : asm volatile (&quot;&quot; : : : &quot;%xmm12&quot;, &quot;%xmm13&quot;, &quot;%xmm14&quot;, &quot;%xmm15&quot;);
<span class="lineNum"> 250 </span> : #endif
<span class="lineNum"> 251 </span> : #endif
<span class="lineNum"> 252 </span> : }
<span class="lineNum"> 253 </span> : #endif
<span class="lineNum"> 254 </span> :
<span class="lineNum"> 255 </span> : #ifdef CONFIG_AVX2
<span class="lineNum"> 256 </span> : static __always_inline void raid_avx_begin(void)
<span class="lineNum"> 257 </span> : {
<span class="lineNum"> 258 </span> : raid_sse_begin();
<span class="lineNum"> 259 </span> : }
<span class="lineNum"> 260 </span> :
<span class="lineNum"> 261 </span> : static __always_inline void raid_avx_end(void)
<span class="lineNum"> 262 </span> : {
<span class="lineNum"> 263 </span> : raid_sse_end();
<span class="lineNum"> 264 </span> :
<span class="lineNum"> 265 </span> : /* reset the upper part of the ymm registers */
<span class="lineNum"> 266 </span> : /* to avoid the 70 clocks penality on the next */
<span class="lineNum"> 267 </span> : /* xmm register use */
<span class="lineNum"> 268 </span><span class="lineCov"> 19674 : asm volatile (&quot;vzeroupper&quot; : : : &quot;memory&quot;);</span>
<span class="lineNum"> 269 </span> : }
<span class="lineNum"> 270 </span> : #endif
<span class="lineNum"> 271 </span> : #endif /* CONFIG_X86 */
<span class="lineNum"> 272 </span> :
<span class="lineNum"> 273 </span> : #endif
<span class="lineNum"> 274 </span> :
</pre>
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