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429 lines
14 KiB
C
429 lines
14 KiB
C
// SPDX-License-Identifier: GPL-3.0-or-later
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// Copyright (C) 2013 Andrea Mazzoleni
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#include "internal.h"
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#include "gf.h"
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#include "cpu.h"
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#ifdef CONFIG_X86
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/* ================================================================
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* Optimizations notes
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* ================================================================
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*
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* For x86 optimizations you can see:
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*
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* Software optimization resources
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* http://www.agner.org/optimize/
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*
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* x86, x64 Instruction Latency, Memory Latency and CPUID dumps
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* http://users.atw.hu/instlatx64/
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*
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* Optimization notes:
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* - Cache Line Sizing: Intentionally don't process more than 64 bytes
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* because 64 is the typical cache block. Processing 128 bytes or more
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* doesn't increase performance, and in some cases it even decreases it.
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* - Register Pressure: Processing exactly 64 bytes perfectly balances
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* the SIMD register file. It allows 128-bit architectures (SSE/NEON)
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* to hold 4 data vectors while keeping all necessary GF constants and
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* masks in the remaining registers, avoiding slow stack spills.
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* - Write-Combining Buffers: The final write of the P,Q,R,S,T parities
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* always uses non-temporal stores (movntdq), even for writes smaller
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* than the cache line, as the CPU has enough write-combining buffers
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* to aggregate the sequential streams and avoid the RFO (Read-For-Ownership)
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* memory penalty.
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* - Parity Accumulator Locality: The outer loop iterates by block size,
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* and the inner loop iterates by disk. This guarantees that the running
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* parity accumulators never leave the CPU's SIMD registers during the
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* computation.
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* - D0 Cauchy Bypass: The final disk processed (D0) always has a
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* coefficient of 1 for all parities. It is handled separately to bypass
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* the expensive Cauchy matrix lookup and `pshufb` multiplications.
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* - Pipeline Dependency Breaking: Galois Field doubling (Horner's method
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* multiplication by 2) is strategically placed relative to the XOR
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* operations to break serial dependency chains. This allows the CPU's
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* out-of-order execution engine to hide the latency of the GF math
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* behind memory loads.
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*/
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/*
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* ================================================================
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* RAID Parity Generation: Q-Parity Horner's Method Implementations
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* ================================================================
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*
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* This file implements different strategies for computing the Q parity.
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* Q parity requires scaling each data disk by a descending power of 2
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* in the Galois Field:
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*
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* Q = (D_l * 2^l) + (D_{l-1} * 2^{l-1}) + ... + (D_1 * 2^1) + (D_0 * 1)
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*
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* To efficiently calculate this sequentially using SIMD instructions, we
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* use Horner's method. Depending on hardware architecture and whether we
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* need to optimize out the final Cauchy matrix multiplication for D0, the
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* "multiply by 2" operation can be positioned in three distinct ways:
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*
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* -------------------------------------------------------------------------
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* CASE 1: Multiplication BEFORE XOR, handling all disks inside the loop
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* -------------------------------------------------------------------------
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* Used in GEN2 (RAID6) where all disks can be processed uniformly.
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* The accumulator is doubled BEFORE adding the current disk. Because the
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* loop runs all the way down to D0 (d >= 0), the final disk is XORed into
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* the accumulator and the loop terminates. This naturally leaves D0 with
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* a coefficient of 1, as it escapes the doubling step.
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*
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* Simplified Code:
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* Q = D_l;
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* for (d = l - 1; d >= 0; --d) {
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* Q = Q * 2; // Scale accumulator
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* Q = Q ^ D_d; // Add current disk
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* }
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*
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* -------------------------------------------------------------------------
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* CASE 2: Multiplication BEFORE XOR, handling D0 separately
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* -------------------------------------------------------------------------
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* Used in GEN3/GEN4 when the loop contains expensive operations (like
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* SSSE3 pshufb for Cauchy matrices) that we want to skip for the very
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* last disk (which only requires coefficient 1). The Q-parity logic is
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* identical to CASE 1, but the final iteration for D0 is unrolled.
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*
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* Simplified Code:
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* Q = D_l;
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* for (d = l - 1; d > 0; --d) {
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* Q = Q * 2; // Scale accumulator
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* Q = Q ^ D_d; // Add current disk
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* }
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*
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* // Final disk (D0) processed outside the loop to skip Cauchy math
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* Q = Q * 2;
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* Q = Q ^ D_0;
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*/
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/*
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* GEN1 (RAID5 with xor) SSE2 implementation
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*/
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void raid_gen1_sse2(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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raid_sse_begin();
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for (i = 0; i < size; i += 64) {
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asm volatile ("movdqa %0,%%xmm0" : : "m" (v[0][i]));
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asm volatile ("movdqa %0,%%xmm1" : : "m" (v[0][i + 16]));
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asm volatile ("movdqa %0,%%xmm2" : : "m" (v[0][i + 32]));
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asm volatile ("movdqa %0,%%xmm3" : : "m" (v[0][i + 48]));
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for (d = 1; d <= l; ++d) {
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asm volatile ("pxor %0,%%xmm0" : : "m" (v[d][i]));
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asm volatile ("pxor %0,%%xmm1" : : "m" (v[d][i + 16]));
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asm volatile ("pxor %0,%%xmm2" : : "m" (v[d][i + 32]));
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asm volatile ("pxor %0,%%xmm3" : : "m" (v[d][i + 48]));
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}
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asm volatile ("movntdq %%xmm0,%0" : "=m" (p[i]));
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asm volatile ("movntdq %%xmm1,%0" : "=m" (p[i + 16]));
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asm volatile ("movntdq %%xmm2,%0" : "=m" (p[i + 32]));
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asm volatile ("movntdq %%xmm3,%0" : "=m" (p[i + 48]));
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}
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raid_sse_end();
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}
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/*
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* GEN2 (RAID6 with powers of 2) SSE2 implementation
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*/
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void raid_gen2_sse2(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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uint8_t *q;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd + 1];
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raid_sse_begin();
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asm volatile ("movdqa %0,%%xmm7" : : "m" (gfconst16.poly[0]));
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for (i = 0; i < size; i += 32) {
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asm volatile ("movdqa %0,%%xmm0" : : "m" (v[l][i]));
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asm volatile ("movdqa %0,%%xmm1" : : "m" (v[l][i + 16]));
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asm volatile ("movdqa %xmm0,%xmm2");
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asm volatile ("movdqa %xmm1,%xmm3");
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for (d = l - 1; d >= 0; --d) {
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/* scale by 2 before adding the current disk so the first (last processed) disk with factor 1 avoids doubling */
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asm volatile ("pxor %xmm4,%xmm4");
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asm volatile ("pxor %xmm5,%xmm5");
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asm volatile ("pcmpgtb %xmm2,%xmm4");
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asm volatile ("pcmpgtb %xmm3,%xmm5");
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asm volatile ("paddb %xmm2,%xmm2");
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asm volatile ("paddb %xmm3,%xmm3");
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asm volatile ("pand %xmm7,%xmm4");
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asm volatile ("pand %xmm7,%xmm5");
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asm volatile ("pxor %xmm4,%xmm2");
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asm volatile ("pxor %xmm5,%xmm3");
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asm volatile ("movdqa %0,%%xmm4" : : "m" (v[d][i]));
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asm volatile ("movdqa %0,%%xmm5" : : "m" (v[d][i + 16]));
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asm volatile ("pxor %xmm4,%xmm0");
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asm volatile ("pxor %xmm5,%xmm1");
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asm volatile ("pxor %xmm4,%xmm2");
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asm volatile ("pxor %xmm5,%xmm3");
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}
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asm volatile ("movntdq %%xmm0,%0" : "=m" (p[i]));
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asm volatile ("movntdq %%xmm1,%0" : "=m" (p[i + 16]));
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asm volatile ("movntdq %%xmm2,%0" : "=m" (q[i]));
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asm volatile ("movntdq %%xmm3,%0" : "=m" (q[i + 16]));
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}
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raid_sse_end();
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}
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#ifdef CONFIG_X86_64
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/*
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* GEN2 (RAID6 with powers of 2) SSE2 implementation
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*
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* Note that it uses 16 registers, meaning that x64 is required.
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*/
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void raid_gen2_sse2ext(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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uint8_t *q;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd + 1];
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raid_sse_begin();
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asm volatile ("movdqa %0,%%xmm15" : : "m" (gfconst16.poly[0]));
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for (i = 0; i < size; i += 64) {
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asm volatile ("movdqa %0,%%xmm0" : : "m" (v[l][i]));
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asm volatile ("movdqa %0,%%xmm1" : : "m" (v[l][i + 16]));
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asm volatile ("movdqa %0,%%xmm2" : : "m" (v[l][i + 32]));
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asm volatile ("movdqa %0,%%xmm3" : : "m" (v[l][i + 48]));
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asm volatile ("movdqa %xmm0,%xmm4");
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asm volatile ("movdqa %xmm1,%xmm5");
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asm volatile ("movdqa %xmm2,%xmm6");
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asm volatile ("movdqa %xmm3,%xmm7");
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for (d = l - 1; d >= 0; --d) {
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/* scale by 2 before adding the current disk so the first (last processed) disk with factor 1 avoids doubling */
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asm volatile ("pxor %xmm8,%xmm8");
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asm volatile ("pxor %xmm9,%xmm9");
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asm volatile ("pxor %xmm10,%xmm10");
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asm volatile ("pxor %xmm11,%xmm11");
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asm volatile ("pcmpgtb %xmm4,%xmm8");
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asm volatile ("pcmpgtb %xmm5,%xmm9");
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asm volatile ("pcmpgtb %xmm6,%xmm10");
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asm volatile ("pcmpgtb %xmm7,%xmm11");
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asm volatile ("paddb %xmm4,%xmm4");
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asm volatile ("paddb %xmm5,%xmm5");
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asm volatile ("paddb %xmm6,%xmm6");
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asm volatile ("paddb %xmm7,%xmm7");
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asm volatile ("pand %xmm15,%xmm8");
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asm volatile ("pand %xmm15,%xmm9");
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asm volatile ("pand %xmm15,%xmm10");
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asm volatile ("pand %xmm15,%xmm11");
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asm volatile ("pxor %xmm8,%xmm4");
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asm volatile ("pxor %xmm9,%xmm5");
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asm volatile ("pxor %xmm10,%xmm6");
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asm volatile ("pxor %xmm11,%xmm7");
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asm volatile ("movdqa %0,%%xmm8" : : "m" (v[d][i]));
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asm volatile ("movdqa %0,%%xmm9" : : "m" (v[d][i + 16]));
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asm volatile ("movdqa %0,%%xmm10" : : "m" (v[d][i + 32]));
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asm volatile ("movdqa %0,%%xmm11" : : "m" (v[d][i + 48]));
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asm volatile ("pxor %xmm8,%xmm0");
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asm volatile ("pxor %xmm9,%xmm1");
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asm volatile ("pxor %xmm10,%xmm2");
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asm volatile ("pxor %xmm11,%xmm3");
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asm volatile ("pxor %xmm8,%xmm4");
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asm volatile ("pxor %xmm9,%xmm5");
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asm volatile ("pxor %xmm10,%xmm6");
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asm volatile ("pxor %xmm11,%xmm7");
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}
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asm volatile ("movntdq %%xmm0,%0" : "=m" (p[i]));
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asm volatile ("movntdq %%xmm1,%0" : "=m" (p[i + 16]));
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asm volatile ("movntdq %%xmm2,%0" : "=m" (p[i + 32]));
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asm volatile ("movntdq %%xmm3,%0" : "=m" (p[i + 48]));
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asm volatile ("movntdq %%xmm4,%0" : "=m" (q[i]));
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asm volatile ("movntdq %%xmm5,%0" : "=m" (q[i + 16]));
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asm volatile ("movntdq %%xmm6,%0" : "=m" (q[i + 32]));
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asm volatile ("movntdq %%xmm7,%0" : "=m" (q[i + 48]));
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}
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raid_sse_end();
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}
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#endif
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/*
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* GENz (triple parity with powers of 2^-1) SSE2 implementation
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*/
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void raid_genz_sse2(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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uint8_t *q;
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uint8_t *r;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd + 1];
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r = v[nd + 2];
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raid_sse_begin();
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asm volatile ("movdqa %0,%%xmm7" : : "m" (gfconst16.poly[0]));
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asm volatile ("movdqa %0,%%xmm3" : : "m" (gfconst16.half[0]));
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asm volatile ("movdqa %0,%%xmm6" : : "m" (gfconst16.low7[0]));
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for (i = 0; i < size; i += 16) {
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asm volatile ("movdqa %0,%%xmm0" : : "m" (v[l][i]));
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asm volatile ("movdqa %xmm0,%xmm1");
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asm volatile ("movdqa %xmm0,%xmm2");
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for (d = l - 1; d >= 0; --d) {
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asm volatile ("pxor %xmm4,%xmm4");
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asm volatile ("pcmpgtb %xmm1,%xmm4");
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asm volatile ("paddb %xmm1,%xmm1");
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asm volatile ("pand %xmm7,%xmm4");
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asm volatile ("pxor %xmm4,%xmm1");
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asm volatile ("movdqa %xmm2,%xmm4");
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asm volatile ("pxor %xmm5,%xmm5");
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asm volatile ("psllw $7,%xmm4");
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asm volatile ("psrlw $1,%xmm2");
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asm volatile ("pcmpgtb %xmm4,%xmm5");
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asm volatile ("pand %xmm6,%xmm2");
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asm volatile ("pand %xmm3,%xmm5");
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asm volatile ("pxor %xmm5,%xmm2");
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asm volatile ("movdqa %0,%%xmm4" : : "m" (v[d][i]));
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asm volatile ("pxor %xmm4,%xmm0");
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asm volatile ("pxor %xmm4,%xmm1");
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asm volatile ("pxor %xmm4,%xmm2");
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}
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asm volatile ("movntdq %%xmm0,%0" : "=m" (p[i]));
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asm volatile ("movntdq %%xmm1,%0" : "=m" (q[i]));
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asm volatile ("movntdq %%xmm2,%0" : "=m" (r[i]));
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}
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raid_sse_end();
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}
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#ifdef CONFIG_X86_64
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/*
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* GENz (triple parity with powers of 2^-1) SSE2 implementation
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*
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* Note that it uses 16 registers, meaning that x64 is required.
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*/
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void raid_genz_sse2ext(int nd, size_t size, void **vv)
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{
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uint8_t **v = (uint8_t **)vv;
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uint8_t *p;
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uint8_t *q;
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uint8_t *r;
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int d, l;
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size_t i;
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l = nd - 1;
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p = v[nd];
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q = v[nd + 1];
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r = v[nd + 2];
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raid_sse_begin();
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asm volatile ("movdqa %0,%%xmm7" : : "m" (gfconst16.poly[0]));
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asm volatile ("movdqa %0,%%xmm3" : : "m" (gfconst16.half[0]));
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asm volatile ("movdqa %0,%%xmm11" : : "m" (gfconst16.low7[0]));
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for (i = 0; i < size; i += 32) {
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asm volatile ("movdqa %0,%%xmm0" : : "m" (v[l][i]));
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asm volatile ("movdqa %0,%%xmm8" : : "m" (v[l][i + 16]));
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asm volatile ("movdqa %xmm0,%xmm1");
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asm volatile ("movdqa %xmm8,%xmm9");
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asm volatile ("movdqa %xmm0,%xmm2");
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asm volatile ("movdqa %xmm8,%xmm10");
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for (d = l - 1; d >= 0; --d) {
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asm volatile ("movdqa %xmm2,%xmm6");
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asm volatile ("movdqa %xmm10,%xmm14");
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asm volatile ("pxor %xmm4,%xmm4");
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asm volatile ("pxor %xmm12,%xmm12");
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asm volatile ("pxor %xmm5,%xmm5");
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asm volatile ("pxor %xmm13,%xmm13");
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asm volatile ("psllw $7,%xmm6");
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asm volatile ("psllw $7,%xmm14");
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asm volatile ("psrlw $1,%xmm2");
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asm volatile ("psrlw $1,%xmm10");
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asm volatile ("pcmpgtb %xmm1,%xmm4");
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asm volatile ("pcmpgtb %xmm9,%xmm12");
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asm volatile ("pcmpgtb %xmm6,%xmm5");
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asm volatile ("pcmpgtb %xmm14,%xmm13");
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asm volatile ("paddb %xmm1,%xmm1");
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asm volatile ("paddb %xmm9,%xmm9");
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asm volatile ("pand %xmm11,%xmm2");
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asm volatile ("pand %xmm11,%xmm10");
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asm volatile ("pand %xmm7,%xmm4");
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asm volatile ("pand %xmm7,%xmm12");
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asm volatile ("pand %xmm3,%xmm5");
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asm volatile ("pand %xmm3,%xmm13");
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asm volatile ("pxor %xmm4,%xmm1");
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asm volatile ("pxor %xmm12,%xmm9");
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asm volatile ("pxor %xmm5,%xmm2");
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asm volatile ("pxor %xmm13,%xmm10");
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asm volatile ("movdqa %0,%%xmm4" : : "m" (v[d][i]));
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asm volatile ("movdqa %0,%%xmm12" : : "m" (v[d][i + 16]));
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asm volatile ("pxor %xmm4,%xmm0");
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asm volatile ("pxor %xmm4,%xmm1");
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asm volatile ("pxor %xmm4,%xmm2");
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asm volatile ("pxor %xmm12,%xmm8");
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asm volatile ("pxor %xmm12,%xmm9");
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asm volatile ("pxor %xmm12,%xmm10");
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}
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asm volatile ("movntdq %%xmm0,%0" : "=m" (p[i]));
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asm volatile ("movntdq %%xmm8,%0" : "=m" (p[i + 16]));
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asm volatile ("movntdq %%xmm1,%0" : "=m" (q[i]));
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asm volatile ("movntdq %%xmm9,%0" : "=m" (q[i + 16]));
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asm volatile ("movntdq %%xmm2,%0" : "=m" (r[i]));
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asm volatile ("movntdq %%xmm10,%0" : "=m" (r[i + 16]));
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}
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raid_sse_end();
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}
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#endif
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void raid_register_sse2(void)
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{
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if (raid_cpu_has_sse2()) {
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raid_gen_register(RAID_ALGO_CAUCHY_PAR1, "sse2", raid_gen1_sse2, RAID_POLY_ANY);
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raid_gen_register(RAID_ALGO_CAUCHY_PAR2, "sse2", raid_gen2_sse2, RAID_POLY_ANY);
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#ifdef CONFIG_X86_64
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if (!raid_cpu_has_slow_extendedreg())
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raid_gen_register(RAID_ALGO_CAUCHY_PAR2, "sse2e", raid_gen2_sse2ext, RAID_POLY_ANY);
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/* note that raid_cpu_has_slow_extendedreg() doesn't affect vandermonde */
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raid_gen_register(RAID_ALGO_VANDERMONDE_PAR3, "sse2e", raid_genz_sse2ext, RAID_POLY_ANY);
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|
#else
|
|
raid_gen_register(RAID_ALGO_VANDERMONDE_PAR3, "sse2", raid_genz_sse2, RAID_POLY_ANY);
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|