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530 lines
15 KiB
C
530 lines
15 KiB
C
// SPDX-License-Identifier: GPL-3.0-or-later
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// Copyright (C) 2011 Andrea Mazzoleni
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#ifndef __UTIL_H
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#define __UTIL_H
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#include "tommyds/tommytypes.h"
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/****************************************************************************/
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/* memory */
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/**
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* Safe aligned malloc.
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* If no memory is available, it aborts.
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*/
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void* malloc_nofail_align(size_t size, void** freeptr);
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/**
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* Safe aligned malloc. Usable for direct io.
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*/
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void* malloc_nofail_direct(size_t size, void** freeptr);
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/**
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* Safe aligned vector allocation.
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* If no memory is available, it aborts.
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*/
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void** malloc_nofail_vector_align(int n, size_t size, void** freeptr);
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/**
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* Safe page vector allocation. Usable for direct io.
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* If no memory is available, it aborts.
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*/
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void** malloc_nofail_vector_direct(int n, size_t size, void** freeptr);
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/**
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* Test the memory vector for RAM problems.
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* If a problem is found, it crashes.
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*/
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void mtest_vector(int n, size_t size, void** vv);
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/**
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* Compare memory against a repeated byte value.
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*
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* Return <0 if ptr is less than value, 0 if equal, >0 if greater.
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*/
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static __always_inline int membcmp(const void* ptr, uint8_t value, size_t size)
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{
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const uint8_t* p = ptr;
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if (size == 0)
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return 0;
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if (p[0] != value)
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return (int)p[0] - (int)value;
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/*
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* If the buffer contains value up to index k-1, then at offset k-1
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* memcmp compares (p + 1)[k - 1] = p[k] against p[k - 1] = value.
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* The first differing adjacent pair yields the exact sign (p[k] - value).
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*/
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return memcmp(p + 1, p, size - 1);
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}
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/****************************************************************************/
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/* crc */
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/**
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* CRC initial value.
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* Using a not zero value allows to detect a leading run of zeros.
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*/
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#define CRC_IV 0xffffffffU
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/**
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* CRC-32 (Castagnoli) table.
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*/
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extern uint32_t CRC32C_0[256];
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extern uint32_t CRC32C_1[256];
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extern uint32_t CRC32C_2[256];
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extern uint32_t CRC32C_3[256];
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#define CRC32C_X86_64_BLOCK0_SIZE 5456
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#define CRC32C_X86_64_BLOCK1_SIZE 2720
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#define CRC32C_X86_64_BLOCK2_SIZE 1360
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#define CRC32C_X86_64_BLOCK3_SIZE 672
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#define CRC32C_X86_64_BLOCK4_SIZE 336
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#define CRC32C_X86_64_BLOCK5_SIZE 160
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#ifdef CONFIG_X86_64
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extern uint32_t CRC32C_X86_64_SKIP[6][8][16];
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#endif
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#define CRC32C_ARM64_BLOCK0_SIZE 8192
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#define CRC32C_ARM64_BLOCK1_SIZE 4096
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#define CRC32C_ARM64_BLOCK2_SIZE 2048
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#define CRC32C_ARM64_BLOCK3_SIZE 1024
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#define CRC32C_ARM64_BLOCK4_SIZE 512
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#define CRC32C_ARM64_BLOCK5_SIZE 256
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#if CONFIG_ARM_CRC
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extern uint32_t CRC32C_ARM64_SKIP[6][8][16];
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#endif
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/**
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* Advance a raw CRC-32C by a number of zero bytes.
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* Used to combine independent hardware CRC lanes.
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*/
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#if defined(CONFIG_X86_64) || CONFIG_ARM_CRC
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uint32_t crc32c_shift(uint32_t crc, size_t size);
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#endif
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/**
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* Compute the CRC-32 (Castagnoli) without the IV.
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*/
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static inline uint32_t crc32c_gen_plain(uint32_t crc, const unsigned char* ptr, size_t size)
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{
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#if defined(__GNUC__) && !defined(__clang__)
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#pragma GCC unroll 1
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#elif defined(__clang__)
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#pragma unroll 1
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#endif
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while (size >= 4) {
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crc ^= ptr[0] | (uint32_t)ptr[1] << 8 | (uint32_t)ptr[2] << 16 | (uint32_t)ptr[3] << 24;
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crc = CRC32C_3[crc & 0xff] ^ CRC32C_2[(crc >> 8) & 0xff] ^ CRC32C_1[(crc >> 16) & 0xff] ^ CRC32C_0[crc >> 24];
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ptr += 4;
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size -= 4;
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}
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while (size) {
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crc = CRC32C_0[(crc ^ *ptr) & 0xff] ^ (crc >> 8);
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++ptr;
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--size;
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}
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return crc;
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}
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/**
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* Compute the CRC-32 (Castagnoli) without the IV.
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*/
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#if CONFIG_X86
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#ifdef CONFIG_X86_64
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static __always_inline uint32_t crc32c_x86_64_skip(uint32_t crc, const uint32_t table[8][16])
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{
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return table[0][crc & 0xf]
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^ table[1][(crc >> 4) & 0xf]
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^ table[2][(crc >> 8) & 0xf]
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^ table[3][(crc >> 12) & 0xf]
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^ table[4][(crc >> 16) & 0xf]
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^ table[5][(crc >> 20) & 0xf]
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^ table[6][(crc >> 24) & 0xf]
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^ table[7][crc >> 28];
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}
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static __always_inline uint32_t crc32c_x86_64_3lane(uint32_t crc, const unsigned char* ptr, size_t lane_size, const uint32_t table[8][16])
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{
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const unsigned char* ptr0 = ptr;
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const unsigned char* ptr1 = ptr + lane_size;
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const unsigned char* ptr2 = ptr1 + lane_size;
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const unsigned char* end = ptr1;
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uint64_t crc0 = crc;
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uint64_t crc1 = 0;
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uint64_t crc2 = 0;
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/*
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* Keep three dependency chains in flight to hide the CRC32 latency.
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* Lane sizes are multiples of 16 to avoid a separate tail loop.
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*/
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while (ptr0 < end) {
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asm volatile ("crc32q %1, %0\n" : "+r" (crc0) : "m" (*(const uint64_t*)ptr0));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc1) : "m" (*(const uint64_t*)ptr1));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc2) : "m" (*(const uint64_t*)ptr2));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc0) : "m" (*(const uint64_t*)(ptr0 + 8)));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc1) : "m" (*(const uint64_t*)(ptr1 + 8)));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc2) : "m" (*(const uint64_t*)(ptr2 + 8)));
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ptr0 += 16;
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ptr1 += 16;
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ptr2 += 16;
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}
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crc = crc32c_x86_64_skip((uint32_t)crc0, table) ^ (uint32_t)crc1;
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return crc32c_x86_64_skip(crc, table) ^ (uint32_t)crc2;
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}
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#endif
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static __always_inline uint32_t crc32c_x86_plain(uint32_t crc, const unsigned char* ptr, size_t size)
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{
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#ifdef CONFIG_X86_64
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uint64_t crc64 = crc;
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if (size >= 3 * CRC32C_X86_64_BLOCK5_SIZE) {
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while (size >= 3 * CRC32C_X86_64_BLOCK0_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK0_SIZE, CRC32C_X86_64_SKIP[0]);
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ptr += 3 * CRC32C_X86_64_BLOCK0_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK0_SIZE;
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}
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while (size >= 3 * CRC32C_X86_64_BLOCK1_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK1_SIZE, CRC32C_X86_64_SKIP[1]);
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ptr += 3 * CRC32C_X86_64_BLOCK1_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK1_SIZE;
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}
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while (size >= 3 * CRC32C_X86_64_BLOCK2_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK2_SIZE, CRC32C_X86_64_SKIP[2]);
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ptr += 3 * CRC32C_X86_64_BLOCK2_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK2_SIZE;
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}
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while (size >= 3 * CRC32C_X86_64_BLOCK3_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK3_SIZE, CRC32C_X86_64_SKIP[3]);
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ptr += 3 * CRC32C_X86_64_BLOCK3_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK3_SIZE;
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}
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while (size >= 3 * CRC32C_X86_64_BLOCK4_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK4_SIZE, CRC32C_X86_64_SKIP[4]);
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ptr += 3 * CRC32C_X86_64_BLOCK4_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK4_SIZE;
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}
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while (size >= 3 * CRC32C_X86_64_BLOCK5_SIZE) {
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crc64 = crc32c_x86_64_3lane((uint32_t)crc64, ptr, CRC32C_X86_64_BLOCK5_SIZE, CRC32C_X86_64_SKIP[5]);
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ptr += 3 * CRC32C_X86_64_BLOCK5_SIZE;
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size -= 3 * CRC32C_X86_64_BLOCK5_SIZE;
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}
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}
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while (size >= 16) {
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asm volatile ("crc32q %1, %0\n" : "+r" (crc64) : "m" (*(const uint64_t*)ptr));
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asm volatile ("crc32q %1, %0\n" : "+r" (crc64) : "m" (*(const uint64_t*)(ptr + 8)));
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ptr += 16;
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size -= 16;
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}
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if (size >= 8) {
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asm volatile ("crc32q %1, %0\n" : "+r" (crc64) : "m" (*(const uint64_t*)ptr));
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ptr += 8;
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size -= 8;
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}
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crc = (uint32_t)crc64;
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#else
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while (size >= 16) {
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)ptr));
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)(ptr + 4)));
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)(ptr + 8)));
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)(ptr + 12)));
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ptr += 16;
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size -= 16;
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}
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if (size >= 8) {
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)ptr));
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)(ptr + 4)));
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ptr += 8;
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size -= 8;
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}
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#endif
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if (size >= 4) {
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asm volatile ("crc32l %1, %0\n" : "+r" (crc) : "m" (*(const uint32_t*)ptr));
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ptr += 4;
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size -= 4;
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}
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if (size >= 2) {
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asm volatile ("crc32w %1, %0\n" : "+r" (crc) : "m" (*(const uint16_t*)ptr));
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ptr += 2;
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size -= 2;
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}
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if (size) {
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asm volatile ("crc32b %1, %0\n" : "+r" (crc) : "m" (*ptr));
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}
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return crc;
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}
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#endif
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#if CONFIG_ARM_CRC
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static __always_inline uint32_t crc32c_arm64_skip(uint32_t crc, const uint32_t table[8][16])
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{
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return table[0][crc & 0xf]
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^ table[1][(crc >> 4) & 0xf]
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^ table[2][(crc >> 8) & 0xf]
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^ table[3][(crc >> 12) & 0xf]
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^ table[4][(crc >> 16) & 0xf]
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^ table[5][(crc >> 20) & 0xf]
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^ table[6][(crc >> 24) & 0xf]
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^ table[7][crc >> 28];
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}
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static __always_inline uint32_t crc32c_arm64_2lane(uint32_t crc, const unsigned char* ptr, size_t lane_size, const uint32_t table[8][16])
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{
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const unsigned char* ptr0 = ptr;
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const unsigned char* ptr1 = ptr + lane_size;
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const unsigned char* end = ptr1;
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uint32_t crc0 = crc;
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uint32_t crc1 = 0;
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/*
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* Keep two dependency chains in flight to hide the CRC32 latency.
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*/
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while (ptr0 < end) {
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uint64_t val00;
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uint64_t val01;
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uint64_t val02;
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uint64_t val03;
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uint64_t val10;
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uint64_t val11;
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uint64_t val12;
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uint64_t val13;
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__builtin_memcpy(&val00, ptr0, 8);
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__builtin_memcpy(&val10, ptr1, 8);
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__builtin_memcpy(&val01, ptr0 + 8, 8);
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__builtin_memcpy(&val11, ptr1 + 8, 8);
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__builtin_memcpy(&val02, ptr0 + 16, 8);
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__builtin_memcpy(&val12, ptr1 + 16, 8);
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__builtin_memcpy(&val03, ptr0 + 24, 8);
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__builtin_memcpy(&val13, ptr1 + 24, 8);
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc0) : "r" (val00));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc1) : "r" (val10));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc0) : "r" (val01));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc1) : "r" (val11));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc0) : "r" (val02));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc1) : "r" (val12));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc0) : "r" (val03));
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc1) : "r" (val13));
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ptr0 += 32;
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ptr1 += 32;
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}
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return crc32c_arm64_skip(crc0, table) ^ crc1;
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}
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static __always_inline uint32_t crc32c_arm64_plain(uint32_t crc, const unsigned char* ptr, size_t size)
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{
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if (size >= 2 * CRC32C_ARM64_BLOCK5_SIZE) {
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while (size >= 2 * CRC32C_ARM64_BLOCK0_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK0_SIZE, CRC32C_ARM64_SKIP[0]);
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ptr += 2 * CRC32C_ARM64_BLOCK0_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK0_SIZE;
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}
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while (size >= 2 * CRC32C_ARM64_BLOCK1_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK1_SIZE, CRC32C_ARM64_SKIP[1]);
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ptr += 2 * CRC32C_ARM64_BLOCK1_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK1_SIZE;
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}
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while (size >= 2 * CRC32C_ARM64_BLOCK2_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK2_SIZE, CRC32C_ARM64_SKIP[2]);
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ptr += 2 * CRC32C_ARM64_BLOCK2_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK2_SIZE;
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}
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while (size >= 2 * CRC32C_ARM64_BLOCK3_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK3_SIZE, CRC32C_ARM64_SKIP[3]);
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ptr += 2 * CRC32C_ARM64_BLOCK3_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK3_SIZE;
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}
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while (size >= 2 * CRC32C_ARM64_BLOCK4_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK4_SIZE, CRC32C_ARM64_SKIP[4]);
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ptr += 2 * CRC32C_ARM64_BLOCK4_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK4_SIZE;
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}
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while (size >= 2 * CRC32C_ARM64_BLOCK5_SIZE) {
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crc = crc32c_arm64_2lane(crc, ptr, CRC32C_ARM64_BLOCK5_SIZE, CRC32C_ARM64_SKIP[5]);
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ptr += 2 * CRC32C_ARM64_BLOCK5_SIZE;
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size -= 2 * CRC32C_ARM64_BLOCK5_SIZE;
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}
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}
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while (size >= 8) {
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uint64_t val;
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__builtin_memcpy(&val, ptr, 8);
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asm volatile ("crc32cx %w0, %w0, %x1\n" : "+r" (crc) : "r" (val));
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ptr += 8;
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size -= 8;
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}
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if (size >= 4) {
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uint32_t val;
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__builtin_memcpy(&val, ptr, 4);
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asm volatile ("crc32cw %w0, %w0, %w1\n" : "+r" (crc) : "r" (val));
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ptr += 4;
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size -= 4;
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}
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while (size) {
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asm volatile ("crc32cb %w0, %w0, %w1\n" : "+r" (crc) : "r" (*ptr));
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++ptr;
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--size;
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}
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return crc;
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}
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#endif
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/**
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* Compute the CRC-32 (Castagnoli)
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*/
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extern uint32_t (*crc32c)(uint32_t crc, const unsigned char* ptr, size_t size);
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/**
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* Internal entry points for testing.
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*/
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uint32_t crc32c_gen(uint32_t crc, const unsigned char* ptr, size_t size);
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uint32_t crc32c_x86(uint32_t crc, const unsigned char* ptr, size_t size);
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uint32_t crc32c_arm64(uint32_t crc, const unsigned char* ptr, size_t size);
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/**
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* Initialize the CRC-32 (Castagnoli) support.
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*/
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void crc32c_init(void);
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/****************************************************************************/
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/* hash */
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/**
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* Size of the hash.
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*/
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#define HASH_MAX 16
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/**
|
|
* Hash kinds.
|
|
*/
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|
#define HASH_UNDEFINED 0
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|
#define HASH_MURMUR3 1
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|
#define HASH_SPOOKY2 2
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|
#define HASH_MUSEAIR 3
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|
|
/**
|
|
* Return the hash that is expected to be the fastest in this architecture
|
|
*/
|
|
unsigned membesthash(void);
|
|
|
|
/**
|
|
* Return the name of the hash
|
|
*/
|
|
const char* memhashname(unsigned kind);
|
|
|
|
/**
|
|
* Compute the HASH of a memory buffer.
|
|
* Seed is a 128 bit vector.
|
|
*
|
|
* This is the raw hash primitive. It hashes exactly size bytes and does not
|
|
* apply SnapRAID block semantics.
|
|
*/
|
|
void memhash(unsigned kind, const unsigned char* seed, void* digest, const void* src, size_t size);
|
|
|
|
/**
|
|
* Compute the hash of a SnapRAID data block.
|
|
*
|
|
* logical_size is the number of bytes logically belonging to the file.
|
|
* block_size is the complete zero-padded RAID block size.
|
|
*
|
|
* Legacy hashes preserve their historical semantics and hash only
|
|
* logical_size bytes.
|
|
*
|
|
* MuseAir hashes the complete canonical RAID block, including the zero
|
|
* padding up to block_size.
|
|
*
|
|
* The caller must guarantee that logical_size <= block_size and, when
|
|
* logical_size < block_size, src[logical_size .. block_size-1] == 0.
|
|
*/
|
|
void memhash_block(unsigned kind, const unsigned char* seed, void* digest, const void* src, size_t logical_size, size_t block_size);
|
|
|
|
/**
|
|
* Return !=0 if the hash kind operates on the complete canonical RAID block.
|
|
*
|
|
* Legacy hashes (Murmur3, Spooky2) preserve historical semantics and hash
|
|
* only the logical file bytes.
|
|
* Modern hashes (MuseAir) hash the complete zero-padded RAID block up to
|
|
* block_size.
|
|
*/
|
|
static inline int memhash_is_block(unsigned kind)
|
|
{
|
|
return kind == HASH_MUSEAIR;
|
|
}
|
|
|
|
/**
|
|
* Return the hash name.
|
|
*/
|
|
const char* hash_config_name(unsigned kind);
|
|
|
|
/**
|
|
* Count the number of different bits in the two buffers.
|
|
*/
|
|
unsigned memdiff(const unsigned char* data1, const unsigned char* data2, size_t size);
|
|
|
|
/**
|
|
* Unit test
|
|
*/
|
|
int util_selftest(void);
|
|
|
|
/****************************************************************************/
|
|
/* lock */
|
|
|
|
/**
|
|
* Create and locks the lock file.
|
|
* Return -1 on error, otherwise it's the file handle to pass to lock_unlock().
|
|
*/
|
|
int lock_lock(const char* file);
|
|
|
|
/**
|
|
* Unlock the lock file.
|
|
* Return -1 on error.
|
|
*/
|
|
int lock_unlock(int f);
|
|
|
|
/****************************************************************************/
|
|
/* bitvect */
|
|
|
|
typedef unsigned char bit_vect_t;
|
|
#define BIT_VECT_SIZE (sizeof(bit_vect_t) * 8)
|
|
|
|
static inline size_t bit_vect_size(size_t max)
|
|
{
|
|
return (max / BIT_VECT_SIZE) + ((max % BIT_VECT_SIZE) != 0);
|
|
}
|
|
|
|
static inline void bit_vect_set(bit_vect_t* bit_vect, size_t off)
|
|
{
|
|
bit_vect_t mask = 1 << (off % BIT_VECT_SIZE);
|
|
bit_vect[off / BIT_VECT_SIZE] |= mask;
|
|
}
|
|
|
|
static inline void bit_vect_clear(bit_vect_t* bit_vect, size_t off)
|
|
{
|
|
bit_vect_t mask = 1 << (off % BIT_VECT_SIZE);
|
|
bit_vect[off / BIT_VECT_SIZE] &= ~mask;
|
|
}
|
|
|
|
static inline int bit_vect_test(bit_vect_t* bit_vect, size_t off)
|
|
{
|
|
bit_vect_t mask = 1 << (off % BIT_VECT_SIZE);
|
|
return (bit_vect[off / BIT_VECT_SIZE] & mask) != 0;
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/* muldiv */
|
|
|
|
unsigned muldiv(uint64_t v, uint64_t mul, uint64_t div);
|
|
unsigned muldiv_upper(uint64_t v, uint64_t mul, uint64_t div);
|
|
|
|
#endif
|
|
|