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105 lines
4.6 KiB
C
105 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) 2013 Andrea Mazzoleni
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#ifndef __RAID_MEMORY_H
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#define __RAID_MEMORY_H
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/**
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* Memory alignment provided by raid_malloc().
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*
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* It should guarantee good cache performance everywhere.
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*/
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#define RAID_MALLOC_ALIGN 256
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/*
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* Memory displacement to avoid L1 cache set aliasing and 4K aliasing penalties
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* on contiguous blocks, used by raid_malloc_vector().
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*
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* When allocating a sequence of disk buffers with a size that is a large
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* power of 2 (or multiples of 4KB/2MB), their starting addresses naturally
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* map to the exact same sets in the L1 Data Cache. If these blocks are
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* accessed in parallel during SIMD parity generation, the memory streams
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* will constantly evict each other, resulting in severe cache thrashing.
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*
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* Furthermore, if buffers are separated by exact multiples of 4096 bytes,
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* modern CPUs suffer a "4K Aliasing" penalty. The memory disambiguation unit
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* misidentifies the lower 12-bits of the addresses as a match, attempting
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* invalid Store-to-Load Forwarding which results in a ~20-cycle pipeline flush.
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*
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* To eliminate both bottlenecks, each disk buffer is allocated with a dynamic
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* displacement of (X * 64 bytes). The optimal 'X' balances two hardware rules:
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* 1. L1 Capacity: The cycle of utilized L1 sets must be >= the number of disks.
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* 2. 4K Aliasing: 'X' should be as close to 32 (2048 bytes) as possible to
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* maximize the distance from 4096-byte boundaries.
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*
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* The multiplier 'X' scales dynamically based on the disk count (nd):
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* - nd <= 8 -> 24 * 64: Cycle of 8. Safest distance from 4K boundaries.
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* - nd <= 16 -> 28 * 64: Cycle of 16. Widely disperses memory streams across
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* the cache, preventing hardware prefetcher clustering.
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* - nd <= 32 -> 30 * 64: Cycle of 32. Tighter L1 packing.
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* - nd <= 64 -> 33 * 64: Cycle of 64. 33 and 64 are coprime, guaranteeing up
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* to 64 streams never collide in L1 or trigger 4K stalls.
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*
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* These are the results in MB/s with no displacement:
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*
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* RAID functions used for computing the parity with 'sync':
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* best int8 int32 int64 sse2 sse2e ssse3 ssse3e avx2 avx2e
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* gen1 avx2 14389 26472 42343 64085
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* gen2 avx2 3788 7309 20930 22042 36916
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* genz avx2e 2368 4262 11791 11786 21770
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* gen3 avx2e 809 11249 11913 21937
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* gen4 avx2e 609 8857 9469 17401
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* gen5 avx2e 488 7147 7465 14231
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* gen6 avx2e 398 5828 6381 12196
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*
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* These are the results with a strategic cache line displacement,
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* demonstrating throughput improvements in the order of 20% or more:
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*
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* RAID functions used for computing the parity with 'sync':
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* best int8 int32 int64 sse2 sse2e ssse3 ssse3e avx2 avx2e
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* gen1 avx2 18550 34501 62950 78335
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* gen2 avx2 5410 10080 27334 28502 46921
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* genz avx2e 3161 5083 14741 14704 26404
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* gen3 avx2e 1296 12752 13902 26446
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* gen4 avx2e 975 9757 10893 20598
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* gen5 avx2e 799 7879 8612 16613
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* gen6 avx2e 663 6386 7283 13987
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*/
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unsigned raid_optimal_displacement(int n);
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/**
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* Aligned malloc.
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* Use an alignment suitable for the raid functions.
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*/
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void *raid_malloc(size_t size, void **freeptr);
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/**
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* Arbitrary aligned malloc.
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*/
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void *raid_malloc_align(size_t size, size_t align_size, void **freeptr);
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/**
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* Aligned vector allocation.
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* Use an alignment suitable for the raid functions.
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* Returns a vector of @n pointers, each one pointing to a block of
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* the specified @size.
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*/
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void **raid_malloc_vector(int n, size_t size, void **freeptr);
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/**
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* Arbitrary aligned vector allocation.
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*/
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void **raid_malloc_vector_align(int n, size_t size, size_t align_size, ssize_t displacement_size, ssize_t wrap_size, void **freeptr);
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/**
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* Fills the memory vector with pseudo-random data based on the specified seed.
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*/
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void raid_mrand_vector(unsigned seed, int n, size_t size, void **vv);
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/**
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* Tests the memory vector for RAM problems.
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* If a problem is found, it crashes.
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*/
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int raid_mtest_vector(int n, size_t size, void **vv);
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#endif
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