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https://github.com/amadvance/snapraid.git
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390 lines
12 KiB
C
390 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) 2013 Andrea Mazzoleni
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#ifndef __RAID_INTERNAL_H
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#define __RAID_INTERNAL_H
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/*
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* Supported instruction sets.
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*
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* It may happen that the assembler is too old to support
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* all instructions, even if the architecture supports them.
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* These defines allow to exclude from the build the unsupported ones.
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*
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* If in your project you use a predefined assembler, you can define them
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* using fixed values, instead of using the HAVE_* defines.
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*/
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#if HAVE_CONFIG_H
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/* Includes the project configuration for HAVE_* defines */
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#include "config.h"
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/* If the compiler supports assembly */
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#if HAVE_ASSEMBLY
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/* Autodetect from the compiler */
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#if defined(__i386__)
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#define CONFIG_X86 1
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#define CONFIG_X86_32 1
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#endif
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#if defined(__x86_64__)
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#define CONFIG_X86 1
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#define CONFIG_X86_64 1
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#endif
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#endif
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/* Enables SSE2, SSSE3, AVX2, AVX512BW, GFNI only if the assembler supports it */
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#if HAVE_SSE2
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#define CONFIG_SSE2 1
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#endif
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#if HAVE_SSSE3
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#define CONFIG_SSSE3 1
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#endif
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#if HAVE_AVX2
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#define CONFIG_AVX2 1
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#endif
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#if HAVE_AVX512BW
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#define CONFIG_AVX512BW 1
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#endif
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#if HAVE_AVX512GFNI
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#define CONFIG_AVX512GFNI 1
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#endif
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#else /* if HAVE_CONFIG_H is not defined */
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/* Assume that assembly is always supported */
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#if defined(__i386__)
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#define CONFIG_X86 1
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#define CONFIG_X86_32 1
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#endif
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#if defined(__x86_64__)
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#define CONFIG_X86 1
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#define CONFIG_X86_64 1
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#endif
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/* Assumes that the assembler supports everything */
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#ifdef CONFIG_X86
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#define CONFIG_SSE2 1
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#define CONFIG_SSSE3 1
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#define CONFIG_AVX2 1
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#endif
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#ifdef CONFIG_X86_64
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#define CONFIG_AVX512BW 1
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#define CONFIG_AVX512GFNI 1
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#endif
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#endif
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/*
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* Includes anything required for compatibility.
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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/*
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* Inverse assert.
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*/
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#define BUG_ON(a) assert(!(a))
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/*
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* Forced inline.
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*/
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#ifndef __always_inline
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#define __always_inline inline __attribute__((always_inline))
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#endif
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/*
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* Forced alignment.
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*/
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#ifndef __aligned
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#define __aligned(a) __attribute__((aligned(a)))
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#endif
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/*
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* Align a pointer at the specified size.
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*/
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static __always_inline void *__align_ptr(void *ptr, uintptr_t size)
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{
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uintptr_t offset = (uintptr_t)ptr;
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offset = (offset + size - 1U) & ~(size - 1U);
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return (void *)offset;
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}
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/*
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* Includes the main interface headers.
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*/
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#include "raid.h"
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#include "helper.h"
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/*
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* Internal functions.
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*
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* These are intended to provide external access for testing.
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*/
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void raid_gen_ref(int nd, int np, size_t size, void **vv);
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void raid_invert(uint8_t *M, uint8_t *V, int n);
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void raid_delta_gen(int nr, int *id, int *ip, int nd, size_t size, void **v);
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void raid_rec1of1(int *id, int nd, size_t size, void **v);
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void raid_rec2of2_int8(int *id, int *ip, int nd, size_t size, void **vv);
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void raid_gen1_int32(int nd, size_t size, void **vv);
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void raid_gen1_int64(int nd, size_t size, void **vv);
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void raid_gen1_sse2(int nd, size_t size, void **vv);
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void raid_gen1_avx2(int nd, size_t size, void **vv);
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void raid_gen1_avx512bw(int nd, size_t size, void **vv);
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void raid_gen2_int32(int nd, size_t size, void **vv);
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void raid_gen2_int64(int nd, size_t size, void **vv);
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void raid_gen2_sse2(int nd, size_t size, void **vv);
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void raid_gen2_avx2(int nd, size_t size, void **vv);
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void raid_gen2_sse2ext(int nd, size_t size, void **vv);
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void raid_gen2_avx512bw(int nd, size_t size, void **vv);
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void raid_gen2_avx512gfni(int nd, size_t size, void **vv);
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void raid_genz_int32(int nd, size_t size, void **vv);
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void raid_genz_int64(int nd, size_t size, void **vv);
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void raid_genz_sse2(int nd, size_t size, void **vv);
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void raid_genz_sse2ext(int nd, size_t size, void **vv);
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void raid_genz_avx2ext(int nd, size_t size, void **vv);
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void raid_gen3_int8(int nd, size_t size, void **vv);
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void raid_gen3_ssse3(int nd, size_t size, void **vv);
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void raid_gen3_ssse3ext(int nd, size_t size, void **vv);
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void raid_gen3_avx2ext(int nd, size_t size, void **vv);
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void raid_gen3_avx512bw(int nd, size_t size, void **vv);
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void raid_gen3_avx512gfni(int nd, size_t size, void **vv);
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void raid_gen4_int8(int nd, size_t size, void **vv);
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void raid_gen4_ssse3(int nd, size_t size, void **vv);
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void raid_gen4_ssse3ext(int nd, size_t size, void **vv);
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void raid_gen4_avx2ext(int nd, size_t size, void **vv);
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void raid_gen4_avx512bw(int nd, size_t size, void **vv);
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void raid_gen4_avx512gfni(int nd, size_t size, void **vv);
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void raid_gen5_int8(int nd, size_t size, void **vv);
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void raid_gen5_ssse3(int nd, size_t size, void **vv);
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void raid_gen5_ssse3ext(int nd, size_t size, void **vv);
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void raid_gen5_avx2ext(int nd, size_t size, void **vv);
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void raid_gen5_avx512bw(int nd, size_t size, void **vv);
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void raid_gen5_avx512gfni(int nd, size_t size, void **vv);
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void raid_gen6_int8(int nd, size_t size, void **vv);
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void raid_gen6_ssse3(int nd, size_t size, void **vv);
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void raid_gen6_ssse3ext(int nd, size_t size, void **vv);
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void raid_gen6_avx2ext(int nd, size_t size, void **vv);
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void raid_gen6_avx512bw(int nd, size_t size, void **vv);
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void raid_gen6_avx512gfni(int nd, size_t size, void **vv);
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void raid_rec1_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec2_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_recX_int8(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec1_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec2_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_recX_ssse3(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec1_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec2_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_recX_avx2(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec1_avx512bw(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec2_avx512bw(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_recX_avx512bw(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec1_avx512gfni(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_rec2_avx512gfni(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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void raid_recX_avx512gfni(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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/*
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* Functions for parity computation.
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*
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* These functions compute the parity blocks from the provided data.
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*
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* The number of parities to compute is implicit in the position in the
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* forwarder vector. Position at index #i, computes (#i+1) parities.
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*
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* All these functions give the guarantee that parities are written
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* in order. First parity P, then parity Q, and so on.
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* This allows to specify the same memory buffer for multiple parities
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* knowing that you'll get the latest written one.
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* This characteristic is used by the raid_delta_gen() function to
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* avoid to damage unused parities in recovering.
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*
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* @nd Number of data blocks
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* @size Size of the blocks pointed by @vv. It must be a multiple of 64.
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* @vv Vector of pointers to the blocks of data and parity.
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* It has (@nd + #parities) elements. The starting elements are the blocks
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* for data, following with the parity blocks.
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* Each block has @size bytes.
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*/
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typedef void (raid_gen_fn)(int nd, size_t size, void **vv);
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/*
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* Functions for data recovery.
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*
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* These functions recover data blocks using the specified parity
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* to recompute the missing data.
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*
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* Note that the format of vectors @id/@ip is different than raid_rec().
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* For example, in the vector @ip the first parity is represented with the
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* value 0 and not @nd.
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*
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* @nr Number of failed data blocks to recover.
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* @id[] Vector of @nr indexes of the data blocks to recover.
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* The indexes start from 0. They must be in order.
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* @ip[] Vector of @nr indexes of the parity blocks to use in the recovering.
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* The indexes start from 0. They must be in order.
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* @nd Number of data blocks.
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* @np Number of parity blocks.
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* @size Size of the blocks pointed by @vv. It must be a multiple of 64.
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* @vv Vector of pointers to the blocks of data and parity.
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* It has (@nd + @np) elements. The starting elements are the blocks
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* for data, following with the parity blocks.
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* Each block has @size bytes.
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*/
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typedef void (raid_rec_fn)(int nr, int *id, int *ip, int nd, size_t size, void **vv);
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/**
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* Algorithm indexes
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*
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* To be used with the register and tag functions.
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*/
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#define RAID_ALGO_CAUCHY_PAR1 0
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#define RAID_ALGO_CAUCHY_PAR2 1
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#define RAID_ALGO_CAUCHY_PAR3 2
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#define RAID_ALGO_CAUCHY_PAR4 3
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#define RAID_ALGO_CAUCHY_PAR5 4
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#define RAID_ALGO_CAUCHY_PAR6 5
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#define RAID_ALGO_VANDERMONDE_PAR3 6
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#define RAID_ALGO_MAX 7
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/**
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* Register functions for parity computation and data recovery.
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*
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* Each call overwrites the previous setting. Thus, call it from the
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* slowest to the fastest.
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*
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* @na Algo code of the function. One of RAID_ALGO_*.
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* @tag Descriptive short tag of the implementation, like "sse2", "avx2",...
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* @fn Function to register.
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*/
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void raid_gen_register(int na, const char *tag, raid_gen_fn *fn);
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void raid_rec_register(int na, const char *tag, raid_rec_fn *fn);
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/**
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* Set functions for data recovery.
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*
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* Intended only for testing the recovery function forcing a specific
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* parity generation for the delta step.
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*
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* Each call overwrites the previous setting.
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*
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* @np Number of parities.
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* @fn Function to register.
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*/
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void raid_gen_force(int np, raid_gen_fn *fn);
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/**
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* Register all the functions based on integer variables.
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*/
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void raid_register_int(void);
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/**
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* Register all the functions based on x86 intructions.
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*/
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void raid_register_x86(void);
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/**
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* Register all the functions based on GFNI intructions.
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*/
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void raid_register_avx512gfni(void);
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/*
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* Tag functions.
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*
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* Given the specified algo code, return the tag of the registered function.
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*/
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const char *raid_gen_tag(int na);
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const char *raid_rec_tag(int na);
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/**
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* Basic functionality self test.
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*
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* Returns 0 on success.
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*/
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int raid_selftest(void);
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/*
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* Tables.
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*/
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extern const uint8_t raid_gfmul[256][256] __aligned(256);
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extern const uint8_t raid_gfexp[256] __aligned(256);
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extern const uint8_t raid_gfinv[256] __aligned(256);
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extern const uint8_t raid_gfvandermonde[3][256] __aligned(256);
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extern const uint8_t raid_gfcauchy[6][256] __aligned(256);
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extern const uint8_t raid_gfcauchypshufb[251][4][2][16] __aligned(256);
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extern const uint8_t raid_gfmulpshufb[256][2][16] __aligned(256);
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extern const uint8_t raid_gfcauchycoeff[251][4][16] __aligned(256);
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extern const uint8_t (*raid_gfgen)[256];
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#define gfmul raid_gfmul
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#define gfexp raid_gfexp
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#define gfinv raid_gfinv
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#define gfvandermonde raid_gfvandermonde
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#define gfcauchy raid_gfcauchy
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#define gfgenpshufb raid_gfcauchypshufb
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#define gfmulpshufb raid_gfmulpshufb
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#define gfgencoeff raid_gfcauchycoeff
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#define gfgen raid_gfgen
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/*
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* Assembler blocks.
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*/
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#ifdef CONFIG_X86
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#ifdef CONFIG_SSE2
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static __always_inline void raid_sse_begin(void)
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{
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}
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static __always_inline void raid_sse_end(void)
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{
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/*
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* SSE and AVX code uses non-temporal writes, like MOVNTDQ,
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* that use a weak memory model. To ensure that other processors
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* see correctly the data written, we use a store-store memory
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* barrier at the end of the asm code
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*/
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asm volatile ("sfence" : : : "memory");
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/*
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* Clobbers registers used in the asm code
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* this is required because in the Windows ABI,
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* registers xmm6-xmm15 should be kept by the callee.
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* this clobber list force the compiler to save any
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* register that needs to be saved
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* we check for __SSE2_ because we require that the
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* compiler supports SSE2 registers in the clobber list
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*/
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#ifdef __SSE2__
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asm volatile ("" : : : "%xmm0", "%xmm1", "%xmm2", "%xmm3");
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asm volatile ("" : : : "%xmm4", "%xmm5", "%xmm6", "%xmm7");
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#ifdef CONFIG_X86_64
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asm volatile ("" : : : "%xmm8", "%xmm9", "%xmm10", "%xmm11");
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asm volatile ("" : : : "%xmm12", "%xmm13", "%xmm14", "%xmm15");
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#endif
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#endif
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}
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#endif
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#ifdef CONFIG_AVX2
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static __always_inline void raid_avx_begin(void)
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{
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raid_sse_begin();
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}
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static __always_inline void raid_avx_end(void)
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{
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raid_sse_end();
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/*
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* Reset the upper part of the ymm registers
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* to avoid the 70 clocks penalty on the next
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* xmm register use
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*/
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asm volatile ("vzeroupper" : : : "memory");
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}
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#endif
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#endif /* CONFIG_X86 */
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#endif
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