snapraid/cov/raid/cpu.h.gcov.html
Andrea Mazzoleni a53ac4a175 Auto update
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<td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">raid</a> - cpu.h<span style="font-size: 80%;"> (source / <a href="cpu.h.func-sort-c.html">functions</a>)</span></td>
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<td class="headerItem">Lines:</td>
<td class="headerCovTableEntry">64</td>
<td class="headerCovTableEntry">76</td>
<td class="headerCovTableEntryMed">84.2 %</td>
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<td class="headerItem">Date:</td>
<td class="headerValue">2026-03-15 15:58:19</td>
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<td class="headerItem">Functions:</td>
<td class="headerCovTableEntry">12</td>
<td class="headerCovTableEntry">12</td>
<td class="headerCovTableEntryHi">100.0 %</td>
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<pre class="sourceHeading"> Line data Source code</pre>
<pre class="source">
<a name="1"><span class="lineNum"> 1 </span> : /*</a>
<a name="2"><span class="lineNum"> 2 </span> : * Copyright (C) 2013 Andrea Mazzoleni</a>
<a name="3"><span class="lineNum"> 3 </span> : *</a>
<a name="4"><span class="lineNum"> 4 </span> : * This program is free software: you can redistribute it and/or modify</a>
<a name="5"><span class="lineNum"> 5 </span> : * it under the terms of the GNU General Public License as published by</a>
<a name="6"><span class="lineNum"> 6 </span> : * the Free Software Foundation, either version 2 of the License, or</a>
<a name="7"><span class="lineNum"> 7 </span> : * (at your option) any later version.</a>
<a name="8"><span class="lineNum"> 8 </span> : *</a>
<a name="9"><span class="lineNum"> 9 </span> : * This program is distributed in the hope that it will be useful,</a>
<a name="10"><span class="lineNum"> 10 </span> : * but WITHOUT ANY WARRANTY; without even the implied warranty of</a>
<a name="11"><span class="lineNum"> 11 </span> : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</a>
<a name="12"><span class="lineNum"> 12 </span> : * GNU General Public License for more details.</a>
<a name="13"><span class="lineNum"> 13 </span> : */</a>
<a name="14"><span class="lineNum"> 14 </span> : </a>
<a name="15"><span class="lineNum"> 15 </span> : #ifndef __RAID_CPU_H</a>
<a name="16"><span class="lineNum"> 16 </span> : #define __RAID_CPU_H</a>
<a name="17"><span class="lineNum"> 17 </span> : </a>
<a name="18"><span class="lineNum"> 18 </span> : #ifdef CONFIG_X86</a>
<a name="19"><span class="lineNum"> 19 </span> : </a>
<a name="20"><span class="lineNum"> 20 </span><span class="lineCov"> 2906 : static inline void raid_cpuid(uint32_t func_eax, uint32_t sub_ecx, uint32_t *reg)</span></a>
<a name="21"><span class="lineNum"> 21 </span> : {</a>
<a name="22"><span class="lineNum"> 22 </span><span class="lineCov"> 2906 : asm volatile (</span></a>
<a name="23"><span class="lineNum"> 23 </span> : #if defined(__i386__) &amp;&amp; defined(__PIC__)</a>
<a name="24"><span class="lineNum"> 24 </span> : /* allow compilation in PIC mode saving ebx */</a>
<a name="25"><span class="lineNum"> 25 </span> : &quot;xchgl %%ebx, %1\n&quot;</a>
<a name="26"><span class="lineNum"> 26 </span> : &quot;cpuid\n&quot;</a>
<a name="27"><span class="lineNum"> 27 </span> : &quot;xchgl %%ebx, %1\n&quot;</a>
<a name="28"><span class="lineNum"> 28 </span> : : &quot;=a&quot; (reg[0]), &quot;=r&quot; (reg[1]), &quot;=c&quot; (reg[2]), &quot;=d&quot; (reg[3])</a>
<a name="29"><span class="lineNum"> 29 </span> : : &quot;0&quot; (func_eax), &quot;2&quot; (sub_ecx)</a>
<a name="30"><span class="lineNum"> 30 </span> : #else</a>
<a name="31"><span class="lineNum"> 31 </span> : &quot;cpuid\n&quot;</a>
<a name="32"><span class="lineNum"> 32 </span><span class="lineCov"> 2906 : : &quot;=a&quot; (reg[0]), &quot;=b&quot; (reg[1]), &quot;=c&quot; (reg[2]), &quot;=d&quot; (reg[3])</span></a>
<a name="33"><span class="lineNum"> 33 </span> : : &quot;0&quot; (func_eax), &quot;2&quot; (sub_ecx)</a>
<a name="34"><span class="lineNum"> 34 </span> : #endif</a>
<a name="35"><span class="lineNum"> 35 </span> : );</a>
<a name="36"><span class="lineNum"> 36 </span><span class="lineCov"> 2906 : }</span></a>
<a name="37"><span class="lineNum"> 37 </span> : </a>
<a name="38"><span class="lineNum"> 38 </span><span class="lineCov"> 31 : static inline void raid_xgetbv(uint32_t* reg)</span></a>
<a name="39"><span class="lineNum"> 39 </span> : {</a>
<a name="40"><span class="lineNum"> 40 </span> : /* get the value of the Extended Control Register ecx=0 */</a>
<a name="41"><span class="lineNum"> 41 </span><span class="lineCov"> 31 : asm volatile (</span></a>
<a name="42"><span class="lineNum"> 42 </span> : /* uses a direct encoding of the XGETBV instruction as only recent */</a>
<a name="43"><span class="lineNum"> 43 </span> : /* assemblers support it. */</a>
<a name="44"><span class="lineNum"> 44 </span> : /* the next line is equivalent at: &quot;xgetbv\n&quot; */</a>
<a name="45"><span class="lineNum"> 45 </span> : &quot;.byte 0x0f, 0x01, 0xd0\n&quot;</a>
<a name="46"><span class="lineNum"> 46 </span><span class="lineCov"> 31 : : &quot;=a&quot; (reg[0]), &quot;=d&quot; (reg[3])</span></a>
<a name="47"><span class="lineNum"> 47 </span> : : &quot;c&quot; (0)</a>
<a name="48"><span class="lineNum"> 48 </span> : );</a>
<a name="49"><span class="lineNum"> 49 </span><span class="lineCov"> 31 : }</span></a>
<a name="50"><span class="lineNum"> 50 </span> : </a>
<a name="51"><span class="lineNum"> 51 </span> : #define CPU_VENDOR_MAX 13</a>
<a name="52"><span class="lineNum"> 52 </span> : </a>
<a name="53"><span class="lineNum"> 53 </span><span class="lineCov"> 605 : static inline void raid_cpu_info(char *vendor, unsigned *family, unsigned *model)</span></a>
<a name="54"><span class="lineNum"> 54 </span> : {</a>
<a name="55"><span class="lineNum"> 55 </span> : uint32_t reg[4];</a>
<a name="56"><span class="lineNum"> 56 </span> : unsigned f, ef, m, em;</a>
<a name="57"><span class="lineNum"> 57 </span> : </a>
<a name="58"><span class="lineNum"> 58 </span><span class="lineCov"> 605 : raid_cpuid(0, 0, reg);</span></a>
<a name="59"><span class="lineNum"> 59 </span> : </a>
<a name="60"><span class="lineNum"> 60 </span><span class="lineCov"> 605 : ((uint32_t*)vendor)[0] = reg[1];</span></a>
<a name="61"><span class="lineNum"> 61 </span><span class="lineCov"> 605 : ((uint32_t*)vendor)[1] = reg[3];</span></a>
<a name="62"><span class="lineNum"> 62 </span><span class="lineCov"> 605 : ((uint32_t*)vendor)[2] = reg[2];</span></a>
<a name="63"><span class="lineNum"> 63 </span><span class="lineCov"> 605 : vendor[12] = 0;</span></a>
<a name="64"><span class="lineNum"> 64 </span> : </a>
<a name="65"><span class="lineNum"> 65 </span><span class="lineCov"> 605 : raid_cpuid(1, 0, reg);</span></a>
<a name="66"><span class="lineNum"> 66 </span> : </a>
<a name="67"><span class="lineNum"> 67 </span><span class="lineCov"> 605 : f = (reg[0] &gt;&gt; 8) &amp; 0xF;</span></a>
<a name="68"><span class="lineNum"> 68 </span><span class="lineCov"> 605 : ef = (reg[0] &gt;&gt; 20) &amp; 0xFF;</span></a>
<a name="69"><span class="lineNum"> 69 </span><span class="lineCov"> 605 : m = (reg[0] &gt;&gt; 4) &amp; 0xF;</span></a>
<a name="70"><span class="lineNum"> 70 </span><span class="lineCov"> 605 : em = (reg[0] &gt;&gt; 16) &amp; 0xF;</span></a>
<a name="71"><span class="lineNum"> 71 </span> : </a>
<a name="72"><span class="lineNum"> 72 </span><span class="lineCov"> 605 : if (strcmp(vendor, &quot;AuthenticAMD&quot;) == 0) {</span></a>
<a name="73"><span class="lineNum"> 73 </span><span class="lineNoCov"> 0 : if (f &lt; 15) {</span></a>
<a name="74"><span class="lineNum"> 74 </span><span class="lineNoCov"> 0 : *family = f;</span></a>
<a name="75"><span class="lineNum"> 75 </span><span class="lineNoCov"> 0 : *model = m;</span></a>
<a name="76"><span class="lineNum"> 76 </span> : } else {</a>
<a name="77"><span class="lineNum"> 77 </span><span class="lineNoCov"> 0 : *family = f + ef;</span></a>
<a name="78"><span class="lineNum"> 78 </span><span class="lineNoCov"> 0 : *model = m + (em &lt;&lt; 4);</span></a>
<a name="79"><span class="lineNum"> 79 </span> : }</a>
<a name="80"><span class="lineNum"> 80 </span> : } else {</a>
<a name="81"><span class="lineNum"> 81 </span><span class="lineCov"> 605 : *family = f + ef;</span></a>
<a name="82"><span class="lineNum"> 82 </span><span class="lineCov"> 605 : *model = m + (em &lt;&lt; 4);</span></a>
<a name="83"><span class="lineNum"> 83 </span> : }</a>
<a name="84"><span class="lineNum"> 84 </span><span class="lineCov"> 605 : }</span></a>
<a name="85"><span class="lineNum"> 85 </span> : </a>
<a name="86"><span class="lineNum"> 86 </span><span class="lineCov"> 1297 : static inline int raid_cpu_match_sse(uint32_t cpuid_1_ecx, uint32_t cpuid_1_edx)</span></a>
<a name="87"><span class="lineNum"> 87 </span> : {</a>
<a name="88"><span class="lineNum"> 88 </span> : uint32_t reg[4];</a>
<a name="89"><span class="lineNum"> 89 </span> : </a>
<a name="90"><span class="lineNum"> 90 </span><span class="lineCov"> 1297 : raid_cpuid(1, 0, reg);</span></a>
<a name="91"><span class="lineNum"> 91 </span><span class="lineCov"> 1297 : if ((reg[2] &amp; cpuid_1_ecx) != cpuid_1_ecx)</span></a>
<a name="92"><span class="lineNum"> 92 </span><span class="lineCov"> 18 : return 0;</span></a>
<a name="93"><span class="lineNum"> 93 </span><span class="lineCov"> 1279 : if ((reg[3] &amp; cpuid_1_edx) != cpuid_1_edx)</span></a>
<a name="94"><span class="lineNum"> 94 </span><span class="lineNoCov"> 0 : return 0;</span></a>
<a name="95"><span class="lineNum"> 95 </span> : </a>
<a name="96"><span class="lineNum"> 96 </span><span class="lineCov"> 1279 : return 1;</span></a>
<a name="97"><span class="lineNum"> 97 </span> : }</a>
<a name="98"><span class="lineNum"> 98 </span> : </a>
<a name="99"><span class="lineNum"> 99 </span><span class="lineCov"> 368 : static inline int raid_cpu_match_avx(uint32_t cpuid_1_ecx, uint32_t cpuid_7_ebx, uint32_t xcr0)</span></a>
<a name="100"><span class="lineNum"> 100 </span> : {</a>
<a name="101"><span class="lineNum"> 101 </span> : uint32_t reg[4];</a>
<a name="102"><span class="lineNum"> 102 </span> : </a>
<a name="103"><span class="lineNum"> 103 </span><span class="lineCov"> 368 : raid_cpuid(1, 0, reg);</span></a>
<a name="104"><span class="lineNum"> 104 </span><span class="lineCov"> 368 : if ((reg[2] &amp; cpuid_1_ecx) != cpuid_1_ecx)</span></a>
<a name="105"><span class="lineNum"> 105 </span><span class="lineCov"> 337 : return 0;</span></a>
<a name="106"><span class="lineNum"> 106 </span> : </a>
<a name="107"><span class="lineNum"> 107 </span><span class="lineCov"> 31 : raid_xgetbv(reg);</span></a>
<a name="108"><span class="lineNum"> 108 </span><span class="lineCov"> 31 : if ((reg[0] &amp; xcr0) != xcr0)</span></a>
<a name="109"><span class="lineNum"> 109 </span><span class="lineNoCov"> 0 : return 0;</span></a>
<a name="110"><span class="lineNum"> 110 </span> : </a>
<a name="111"><span class="lineNum"> 111 </span><span class="lineCov"> 31 : raid_cpuid(7, 0, reg);</span></a>
<a name="112"><span class="lineNum"> 112 </span><span class="lineCov"> 31 : if ((reg[1] &amp; cpuid_7_ebx) != cpuid_7_ebx)</span></a>
<a name="113"><span class="lineNum"> 113 </span><span class="lineNoCov"> 0 : return 0;</span></a>
<a name="114"><span class="lineNum"> 114 </span> : </a>
<a name="115"><span class="lineNum"> 115 </span><span class="lineCov"> 31 : return 1;</span></a>
<a name="116"><span class="lineNum"> 116 </span> : }</a>
<a name="117"><span class="lineNum"> 117 </span> : </a>
<a name="118"><span class="lineNum"> 118 </span><span class="lineCov"> 333 : static inline int raid_cpu_has_sse2(void)</span></a>
<a name="119"><span class="lineNum"> 119 </span> : {</a>
<a name="120"><span class="lineNum"> 120 </span> : /*</a>
<a name="121"><span class="lineNum"> 121 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual</a>
<a name="122"><span class="lineNum"> 122 </span> : * 325462-048US September 2013</a>
<a name="123"><span class="lineNum"> 123 </span> : *</a>
<a name="124"><span class="lineNum"> 124 </span> : * 11.6.2 Checking for SSE/SSE2 Support</a>
<a name="125"><span class="lineNum"> 125 </span> : * Before an application attempts to use the SSE and/or SSE2 extensions, it should check</a>
<a name="126"><span class="lineNum"> 126 </span> : * that they are present on the processor:</a>
<a name="127"><span class="lineNum"> 127 </span> : * 1. Check that the processor supports the CPUID instruction. Bit 21 of the EFLAGS</a>
<a name="128"><span class="lineNum"> 128 </span> : * register can be used to check processor's support the CPUID instruction.</a>
<a name="129"><span class="lineNum"> 129 </span> : * 2. Check that the processor supports the SSE and/or SSE2 extensions (true if</a>
<a name="130"><span class="lineNum"> 130 </span> : * CPUID.01H:EDX.SSE[bit 25] = 1 and/or CPUID.01H:EDX.SSE2[bit 26] = 1).</a>
<a name="131"><span class="lineNum"> 131 </span> : */</a>
<a name="132"><span class="lineNum"> 132 </span><span class="lineCov"> 333 : return raid_cpu_match_sse(</span></a>
<a name="133"><span class="lineNum"> 133 </span> : 0,</a>
<a name="134"><span class="lineNum"> 134 </span> : 1 &lt;&lt; 26); /* SSE2 */</a>
<a name="135"><span class="lineNum"> 135 </span> : }</a>
<a name="136"><span class="lineNum"> 136 </span> : </a>
<a name="137"><span class="lineNum"> 137 </span><span class="lineCov"> 643 : static inline int raid_cpu_has_ssse3(void)</span></a>
<a name="138"><span class="lineNum"> 138 </span> : {</a>
<a name="139"><span class="lineNum"> 139 </span> : /*</a>
<a name="140"><span class="lineNum"> 140 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual</a>
<a name="141"><span class="lineNum"> 141 </span> : * 325462-048US September 2013</a>
<a name="142"><span class="lineNum"> 142 </span> : *</a>
<a name="143"><span class="lineNum"> 143 </span> : * 12.7.2 Checking for SSSE3 Support</a>
<a name="144"><span class="lineNum"> 144 </span> : * Before an application attempts to use the SSSE3 extensions, the application should</a>
<a name="145"><span class="lineNum"> 145 </span> : * follow the steps illustrated in Section 11.6.2, &quot;Checking for SSE/SSE2 Support.&quot;</a>
<a name="146"><span class="lineNum"> 146 </span> : * Next, use the additional step provided below:</a>
<a name="147"><span class="lineNum"> 147 </span> : * Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).</a>
<a name="148"><span class="lineNum"> 148 </span> : */</a>
<a name="149"><span class="lineNum"> 149 </span><span class="lineCov"> 643 : return raid_cpu_match_sse(</span></a>
<a name="150"><span class="lineNum"> 150 </span> : 1 &lt;&lt; 9, /* SSSE3 */</a>
<a name="151"><span class="lineNum"> 151 </span> : 1 &lt;&lt; 26); /* SSE2 */</a>
<a name="152"><span class="lineNum"> 152 </span> : }</a>
<a name="153"><span class="lineNum"> 153 </span> : </a>
<a name="154"><span class="lineNum"> 154 </span><span class="lineCov"> 321 : static inline int raid_cpu_has_crc32(void)</span></a>
<a name="155"><span class="lineNum"> 155 </span> : {</a>
<a name="156"><span class="lineNum"> 156 </span> : /*</a>
<a name="157"><span class="lineNum"> 157 </span> : * Intel<65> 64 and IA-32 Architectures Software Developer's Manual</a>
<a name="158"><span class="lineNum"> 158 </span> : * 325462-048US September 2013</a>
<a name="159"><span class="lineNum"> 159 </span> : *</a>
<a name="160"><span class="lineNum"> 160 </span> : * 12.12.3 Checking for SSE4.2 Support</a>
<a name="161"><span class="lineNum"> 161 </span> : * ...</a>
<a name="162"><span class="lineNum"> 162 </span> : * Before an application attempts to use the CRC32 instruction, it must check</a>
<a name="163"><span class="lineNum"> 163 </span> : * that the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1).</a>
<a name="164"><span class="lineNum"> 164 </span> : */</a>
<a name="165"><span class="lineNum"> 165 </span><span class="lineCov"> 321 : return raid_cpu_match_sse(</span></a>
<a name="166"><span class="lineNum"> 166 </span> : 1 &lt;&lt; 20, /* CRC32 */</a>
<a name="167"><span class="lineNum"> 167 </span> : 0);</a>
<a name="168"><span class="lineNum"> 168 </span> : }</a>
<a name="169"><span class="lineNum"> 169 </span> : </a>
<a name="170"><span class="lineNum"> 170 </span><span class="lineCov"> 368 : static inline int raid_cpu_has_avx2(void)</span></a>
<a name="171"><span class="lineNum"> 171 </span> : {</a>
<a name="172"><span class="lineNum"> 172 </span> : /*</a>
<a name="173"><span class="lineNum"> 173 </span> : * Intel Architecture Instruction Set Extensions Programming Reference</a>
<a name="174"><span class="lineNum"> 174 </span> : * 319433-022 October 2014</a>
<a name="175"><span class="lineNum"> 175 </span> : *</a>
<a name="176"><span class="lineNum"> 176 </span> : * 14.3 Detection of AVX instructions</a>
<a name="177"><span class="lineNum"> 177 </span> : * 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)</a>
<a name="178"><span class="lineNum"> 178 </span> : * 2) Issue XGETBV and verify that XCR0[2:1] = `11b' (XMM state and YMM state are enabled by OS).</a>
<a name="179"><span class="lineNum"> 179 </span> : * 3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).</a>
<a name="180"><span class="lineNum"> 180 </span> : * (Step 3 can be done in any order relative to 1 and 2)</a>
<a name="181"><span class="lineNum"> 181 </span> : *</a>
<a name="182"><span class="lineNum"> 182 </span> : * 14.7.1 Detection of AVX2</a>
<a name="183"><span class="lineNum"> 183 </span> : * Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.</a>
<a name="184"><span class="lineNum"> 184 </span> : * Application Software must identify that hardware supports AVX, after that it must</a>
<a name="185"><span class="lineNum"> 185 </span> : * also detect support for AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5].</a>
<a name="186"><span class="lineNum"> 186 </span> : */</a>
<a name="187"><span class="lineNum"> 187 </span><span class="lineCov"> 368 : return raid_cpu_match_avx(</span></a>
<a name="188"><span class="lineNum"> 188 </span> : (1 &lt;&lt; 27) | (1 &lt;&lt; 28), /* OSXSAVE and AVX */</a>
<a name="189"><span class="lineNum"> 189 </span> : 1 &lt;&lt; 5, /* AVX2 */</a>
<a name="190"><span class="lineNum"> 190 </span> : 3 &lt;&lt; 1); /* OS saves XMM and YMM registers */</a>
<a name="191"><span class="lineNum"> 191 </span> : }</a>
<a name="192"><span class="lineNum"> 192 </span> : </a>
<a name="193"><span class="lineNum"> 193 </span> : static inline int raid_cpu_has_avx512bw(void)</a>
<a name="194"><span class="lineNum"> 194 </span> : {</a>
<a name="195"><span class="lineNum"> 195 </span> : /*</a>
<a name="196"><span class="lineNum"> 196 </span> : * Intel Architecture Instruction Set Extensions Programming Reference</a>
<a name="197"><span class="lineNum"> 197 </span> : * 319433-022 October 2014</a>
<a name="198"><span class="lineNum"> 198 </span> : *</a>
<a name="199"><span class="lineNum"> 199 </span> : * 2.2 Detection of 512-bit Instruction Groups of Intel AVX-512 Family</a>
<a name="200"><span class="lineNum"> 200 </span> : * 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use)</a>
<a name="201"><span class="lineNum"> 201 </span> : * 2) Execute XGETBV and verify that XCR0[7:5] = `111b' (OPMASK state, upper 256-bit of</a>
<a name="202"><span class="lineNum"> 202 </span> : * ZMM0-ZMM15 and ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = `11b'</a>
<a name="203"><span class="lineNum"> 203 </span> : * (XMM state and YMM state are enabled by OS).</a>
<a name="204"><span class="lineNum"> 204 </span> : * 3) Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512BW[bit 30] = 1.</a>
<a name="205"><span class="lineNum"> 205 </span> : */</a>
<a name="206"><span class="lineNum"> 206 </span> : </a>
<a name="207"><span class="lineNum"> 207 </span> : /* note that intentionally we don't check for AVX and AVX2 */</a>
<a name="208"><span class="lineNum"> 208 </span> : /* because the documentation doesn't require that */</a>
<a name="209"><span class="lineNum"> 209 </span> : return raid_cpu_match_avx(</a>
<a name="210"><span class="lineNum"> 210 </span> : 1 &lt;&lt; 27, /* XSAVE/XGETBV */</a>
<a name="211"><span class="lineNum"> 211 </span> : (1 &lt;&lt; 16) | (1 &lt;&lt; 30), /* AVX512F and AVX512BW */</a>
<a name="212"><span class="lineNum"> 212 </span> : (3 &lt;&lt; 1) | (7 &lt;&lt; 5)); /* OS saves XMM, YMM and ZMM registers */</a>
<a name="213"><span class="lineNum"> 213 </span> : }</a>
<a name="214"><span class="lineNum"> 214 </span> : </a>
<a name="215"><span class="lineNum"> 215 </span> : /**</a>
<a name="216"><span class="lineNum"> 216 </span> : * Check if it's an Intel Atom CPU.</a>
<a name="217"><span class="lineNum"> 217 </span> : */</a>
<a name="218"><span class="lineNum"> 218 </span><span class="lineCov"> 601 : static inline int raid_cpu_is_atom(unsigned family, unsigned model)</span></a>
<a name="219"><span class="lineNum"> 219 </span> : {</a>
<a name="220"><span class="lineNum"> 220 </span><span class="lineCov"> 601 : if (family != 6)</span></a>
<a name="221"><span class="lineNum"> 221 </span><span class="lineCov"> 3 : return 0;</span></a>
<a name="222"><span class="lineNum"> 222 </span> : </a>
<a name="223"><span class="lineNum"> 223 </span> : /*</a>
<a name="224"><span class="lineNum"> 224 </span> : * x86 Architecture CPUID</a>
<a name="225"><span class="lineNum"> 225 </span> : * http://www.sandpile.org/x86/cpuid.htm</a>
<a name="226"><span class="lineNum"> 226 </span> : *</a>
<a name="227"><span class="lineNum"> 227 </span> : * Intel Atom</a>
<a name="228"><span class="lineNum"> 228 </span> : * 1C (28) Atom (45 nm) with 512 KB on-die L2</a>
<a name="229"><span class="lineNum"> 229 </span> : * 26 (38) Atom (45 nm) with 512 KB on-die L2</a>
<a name="230"><span class="lineNum"> 230 </span> : * 36 (54) Atom (32 nm) with 512 KB on-die L2</a>
<a name="231"><span class="lineNum"> 231 </span> : * 27 (39) Atom (32 nm) with 512 KB on-die L2</a>
<a name="232"><span class="lineNum"> 232 </span> : * 35 (53) Atom (?? nm) with ??? KB on-die L2</a>
<a name="233"><span class="lineNum"> 233 </span> : * 4A (74) Atom 2C (22 nm) 1 MB L2 + PowerVR (TGR)</a>
<a name="234"><span class="lineNum"> 234 </span> : * 5A (90) Atom 4C (22 nm) 2 MB L2 + PowerVR (ANN)</a>
<a name="235"><span class="lineNum"> 235 </span> : * 37 (55) Atom 4C (22 nm) 2 MB L2 + Intel Gen7 (BYT)</a>
<a name="236"><span class="lineNum"> 236 </span> : * 4C (76) Atom 4C (14 nm) 2 MB L2 + Intel Gen8 (BSW)</a>
<a name="237"><span class="lineNum"> 237 </span> : * 5D (93) Atom 4C (28 nm TSMC) 1 MB L2 + Mali (SoFIA)</a>
<a name="238"><span class="lineNum"> 238 </span> : * 4D (77) Atom 8C (22 nm) 4 MB L2 (AVN)</a>
<a name="239"><span class="lineNum"> 239 </span> : * ?? Atom ?C (14 nm) ? MB L2 (DVN)</a>
<a name="240"><span class="lineNum"> 240 </span> : */</a>
<a name="241"><span class="lineNum"> 241 </span><span class="lineCov"> 598 : return model == 28 || model == 38 || model == 54</span></a>
<a name="242"><span class="lineNum"> 242 </span><span class="lineCov"> 598 : || model == 39 || model == 53 || model == 74</span></a>
<a name="243"><span class="lineNum"> 243 </span><span class="lineCov"> 598 : || model == 90 || model == 55 || model == 76</span></a>
<a name="244"><span class="lineNum"> 244 </span><span class="lineCov"> 1196 : || model == 93 || model == 77;</span></a>
<a name="245"><span class="lineNum"> 245 </span> : }</a>
<a name="246"><span class="lineNum"> 246 </span> : </a>
<a name="247"><span class="lineNum"> 247 </span> : /**</a>
<a name="248"><span class="lineNum"> 248 </span> : * Check if the processor has a slow MULT implementation.</a>
<a name="249"><span class="lineNum"> 249 </span> : * If yes, it's better to use a hash not based on multiplication.</a>
<a name="250"><span class="lineNum"> 250 </span> : */</a>
<a name="251"><span class="lineNum"> 251 </span><span class="lineCov"> 4 : static inline int raid_cpu_has_slowmult(void)</span></a>
<a name="252"><span class="lineNum"> 252 </span> : {</a>
<a name="253"><span class="lineNum"> 253 </span> : char vendor[CPU_VENDOR_MAX];</a>
<a name="254"><span class="lineNum"> 254 </span> : unsigned family;</a>
<a name="255"><span class="lineNum"> 255 </span> : unsigned model;</a>
<a name="256"><span class="lineNum"> 256 </span> : </a>
<a name="257"><span class="lineNum"> 257 </span> : /*</a>
<a name="258"><span class="lineNum"> 258 </span> : * In some cases Murmur3 based on MUL instruction,</a>
<a name="259"><span class="lineNum"> 259 </span> : * is a LOT slower than Spooky2 based on SHIFTs.</a>
<a name="260"><span class="lineNum"> 260 </span> : */</a>
<a name="261"><span class="lineNum"> 261 </span><span class="lineCov"> 4 : raid_cpu_info(vendor, &amp;family, &amp;model);</span></a>
<a name="262"><span class="lineNum"> 262 </span> : </a>
<a name="263"><span class="lineNum"> 263 </span><span class="lineCov"> 4 : if (strcmp(vendor, &quot;GenuineIntel&quot;) == 0) {</span></a>
<a name="264"><span class="lineNum"> 264 </span> : /*</a>
<a name="265"><span class="lineNum"> 265 </span> : * Intel Atom (Model 28)</a>
<a name="266"><span class="lineNum"> 266 </span> : * murmur3:378 MB/s, spooky2:3413 MB/s (x86)</a>
<a name="267"><span class="lineNum"> 267 </span> : *</a>
<a name="268"><span class="lineNum"> 268 </span> : * Intel Atom (Model 77)</a>
<a name="269"><span class="lineNum"> 269 </span> : * murmur3:1311 MB/s, spooky2:4056 MB/s (x64)</a>
<a name="270"><span class="lineNum"> 270 </span> : */</a>
<a name="271"><span class="lineNum"> 271 </span><span class="lineCov"> 4 : if (raid_cpu_is_atom(family, model))</span></a>
<a name="272"><span class="lineNum"> 272 </span><span class="lineNoCov"> 0 : return 1;</span></a>
<a name="273"><span class="lineNum"> 273 </span> : }</a>
<a name="274"><span class="lineNum"> 274 </span> : </a>
<a name="275"><span class="lineNum"> 275 </span><span class="lineCov"> 4 : return 0;</span></a>
<a name="276"><span class="lineNum"> 276 </span> : }</a>
<a name="277"><span class="lineNum"> 277 </span> : </a>
<a name="278"><span class="lineNum"> 278 </span> : /**</a>
<a name="279"><span class="lineNum"> 279 </span> : * Check if the processor has a slow extended set of SSE registers.</a>
<a name="280"><span class="lineNum"> 280 </span> : * If yes, it's better to limit the unroll to the firsrt 8 registers.</a>
<a name="281"><span class="lineNum"> 281 </span> : */</a>
<a name="282"><span class="lineNum"> 282 </span><span class="lineCov"> 597 : static inline int raid_cpu_has_slowextendedreg(void)</span></a>
<a name="283"><span class="lineNum"> 283 </span> : {</a>
<a name="284"><span class="lineNum"> 284 </span> : char vendor[CPU_VENDOR_MAX];</a>
<a name="285"><span class="lineNum"> 285 </span> : unsigned family;</a>
<a name="286"><span class="lineNum"> 286 </span> : unsigned model;</a>
<a name="287"><span class="lineNum"> 287 </span> : </a>
<a name="288"><span class="lineNum"> 288 </span> : /*</a>
<a name="289"><span class="lineNum"> 289 </span> : * In some cases the PAR2 implementation using 16 SSE registers</a>
<a name="290"><span class="lineNum"> 290 </span> : * is a LITTLE slower than the one using only the first 8 registers.</a>
<a name="291"><span class="lineNum"> 291 </span> : * This doesn't happen for PARZ.</a>
<a name="292"><span class="lineNum"> 292 </span> : */</a>
<a name="293"><span class="lineNum"> 293 </span><span class="lineCov"> 597 : raid_cpu_info(vendor, &amp;family, &amp;model);</span></a>
<a name="294"><span class="lineNum"> 294 </span> : </a>
<a name="295"><span class="lineNum"> 295 </span><span class="lineCov"> 597 : if (strcmp(vendor, &quot;AuthenticAMD&quot;) == 0) {</span></a>
<a name="296"><span class="lineNum"> 296 </span> : /*</a>
<a name="297"><span class="lineNum"> 297 </span> : * AMD Bulldozer</a>
<a name="298"><span class="lineNum"> 298 </span> : * par2_sse2:4922 MB/s, par2_sse2e:4465 MB/s</a>
<a name="299"><span class="lineNum"> 299 </span> : */</a>
<a name="300"><span class="lineNum"> 300 </span><span class="lineNoCov"> 0 : if (family == 21)</span></a>
<a name="301"><span class="lineNum"> 301 </span><span class="lineNoCov"> 0 : return 1;</span></a>
<a name="302"><span class="lineNum"> 302 </span> : }</a>
<a name="303"><span class="lineNum"> 303 </span> : </a>
<a name="304"><span class="lineNum"> 304 </span><span class="lineCov"> 597 : if (strcmp(vendor, &quot;GenuineIntel&quot;) == 0) {</span></a>
<a name="305"><span class="lineNum"> 305 </span> : /*</a>
<a name="306"><span class="lineNum"> 306 </span> : * Intel Atom (Model 77)</a>
<a name="307"><span class="lineNum"> 307 </span> : * par2_sse2:5686 MB/s, par2_sse2e:5250 MB/s</a>
<a name="308"><span class="lineNum"> 308 </span> : * parz_sse2:3100 MB/s, parz_sse2e:3400 MB/s</a>
<a name="309"><span class="lineNum"> 309 </span> : * par3_sse3:1921 MB/s, par3_sse3e:1813 MB/s</a>
<a name="310"><span class="lineNum"> 310 </span> : * par4_sse3:1175 MB/s, par4_sse3e:1113 MB/s</a>
<a name="311"><span class="lineNum"> 311 </span> : * par5_sse3:876 MB/s, par5_sse3e:675 MB/s</a>
<a name="312"><span class="lineNum"> 312 </span> : * par6_sse3:705 MB/s, par6_sse3e:529 MB/s</a>
<a name="313"><span class="lineNum"> 313 </span> : *</a>
<a name="314"><span class="lineNum"> 314 </span> : * Intel Atom (Model 77) &quot;Avoton C2750&quot;</a>
<a name="315"><span class="lineNum"> 315 </span> : * par2_sse2:5661 MB/s, par2_sse2e:5382 MB/s</a>
<a name="316"><span class="lineNum"> 316 </span> : * parz_sse2:3110 MB/s, parz_sse2e:3450 MB/s</a>
<a name="317"><span class="lineNum"> 317 </span> : * par3_sse3:1769 MB/s, par3_sse3e:1856 MB/s</a>
<a name="318"><span class="lineNum"> 318 </span> : * par4_sse3:1221 MB/s, par4_sse3e:1141 MB/s</a>
<a name="319"><span class="lineNum"> 319 </span> : * par5_sse3:910 MB/s, par5_sse3e:675 MB/s</a>
<a name="320"><span class="lineNum"> 320 </span> : * par6_sse3:720 MB/s, par6_sse3e:534 MB/s</a>
<a name="321"><span class="lineNum"> 321 </span> : */</a>
<a name="322"><span class="lineNum"> 322 </span><span class="lineCov"> 597 : if (raid_cpu_is_atom(family, model))</span></a>
<a name="323"><span class="lineNum"> 323 </span><span class="lineNoCov"> 0 : return 1;</span></a>
<a name="324"><span class="lineNum"> 324 </span> : }</a>
<a name="325"><span class="lineNum"> 325 </span> : </a>
<a name="326"><span class="lineNum"> 326 </span><span class="lineCov"> 597 : return 0;</span></a>
<a name="327"><span class="lineNum"> 327 </span> : }</a>
<a name="328"><span class="lineNum"> 328 </span> : #endif</a>
<a name="329"><span class="lineNum"> 329 </span> : </a>
<a name="330"><span class="lineNum"> 330 </span> : #endif</a>
<a name="331"><span class="lineNum"> 331 </span> : </a>
</pre>
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