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468 lines
13 KiB
C
468 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) 2013 Andrea Mazzoleni
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#ifndef RAID_CPU_H
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#define RAID_CPU_H
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#ifdef CONFIG_X86
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static inline void raid_cpuid(uint32_t func_eax, uint32_t sub_ecx, uint32_t *reg)
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{
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asm volatile (
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#if defined(__i386__) && defined(__PIC__)
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/* allow compilation in PIC mode saving ebx */
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"xchgl %%ebx, %1\n"
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"cpuid\n"
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"xchgl %%ebx, %1\n"
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: "=a" (reg[0]), "=r" (reg[1]), "=c" (reg[2]), "=d" (reg[3])
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: "0" (func_eax), "2" (sub_ecx)
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#else
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"cpuid\n"
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: "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3])
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: "0" (func_eax), "2" (sub_ecx)
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#endif
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);
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}
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static inline void raid_xgetbv(uint32_t *reg)
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{
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/* get the value of the Extended Control Register ecx=0 */
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asm volatile (
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/*
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* Uses a direct encoding of the XGETBV instruction as only recent
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* assemblers support it.
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* the next line is equivalent to: "xgetbv\n"
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*/
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".byte 0x0f, 0x01, 0xd0\n"
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: "=a" (reg[0]), "=d" (reg[3])
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: "c" (0)
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);
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}
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#define CPU_VENDOR_MAX 13
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static inline void raid_cpu_info(char *vendor, unsigned *family, unsigned *model)
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{
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uint32_t reg[4];
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unsigned f, ef, m, em;
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raid_cpuid(0, 0, reg);
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memcpy(vendor + 0, ®[1], 4);
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memcpy(vendor + 4, ®[3], 4);
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memcpy(vendor + 8, ®[2], 4);
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vendor[12] = 0;
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raid_cpuid(1, 0, reg);
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f = (reg[0] >> 8) & 0xF;
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ef = (reg[0] >> 20) & 0xFF;
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m = (reg[0] >> 4) & 0xF;
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em = (reg[0] >> 16) & 0xF;
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if (strcmp(vendor, "AuthenticAMD") == 0) {
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if (f < 15) {
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*family = f;
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*model = m;
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} else {
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*family = f + ef;
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*model = m + (em << 4);
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}
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} else {
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*family = f + ef;
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*model = m + (em << 4);
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}
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}
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static inline int raid_cpu_match_sse(uint32_t leaf_1_ecx, uint32_t leaf_1_edx)
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{
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uint32_t reg[4];
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raid_cpuid(1, 0, reg);
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if ((reg[2] & leaf_1_ecx) != leaf_1_ecx)
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return 0;
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if ((reg[3] & leaf_1_edx) != leaf_1_edx)
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return 0;
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return 1;
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}
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static inline int raid_cpu_match_avx(uint32_t leaf_1_ecx, uint32_t leaf_7_ebx, uint32_t leaf_7_ecx, uint32_t xcr0)
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{
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uint32_t reg[4];
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/* check that leaf 7 is supported */
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raid_cpuid(0, 0, reg);
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if (reg[0] < 7)
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return 0;
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raid_cpuid(1, 0, reg);
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if ((reg[2] & leaf_1_ecx) != leaf_1_ecx)
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return 0;
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raid_xgetbv(reg);
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if ((reg[0] & xcr0) != xcr0)
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return 0;
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raid_cpuid(7, 0, reg);
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if ((reg[1] & leaf_7_ebx) != leaf_7_ebx)
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return 0;
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if ((reg[2] & leaf_7_ecx) != leaf_7_ecx)
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return 0;
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return 1;
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}
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static inline int raid_cpu_has_sse2(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 11.6.2 Checking for SSE/SSE2 Support
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* Before an application attempts to use the SSE and/or SSE2 extensions, it should check
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* that they are present on the processor:
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* 1. Check that the processor supports the CPUID instruction. Bit 21 of the EFLAGS
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* register can be used to check if the processor supports the CPUID instruction.
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* 2. Check that the processor supports the SSE and/or SSE2 extensions (true if
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* CPUID.01H:EDX.SSE[bit 25] = 1 and/or CPUID.01H:EDX.SSE2[bit 26] = 1).
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*/
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uint32_t leaf_1_edx = 1 << 26; /* SSE2 */
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return raid_cpu_match_sse(0, leaf_1_edx);
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}
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static inline int raid_cpu_has_clflush(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* CPUID - CPU Identification
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*
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* Check that the processor supports CLFLUSH (true if CPUID.01H:EDX.CLFSH[bit 19] = 1).
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*/
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uint32_t leaf_1_edx = 1 << 19; /* CLFLUSH */
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return raid_cpu_match_sse(0, leaf_1_edx);
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}
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static inline int raid_cpu_has_clflushopt(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* CPUID - CPU Identification
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*
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* Check that the processor supports CLFLUSHOPT (true if CPUID.07H.00H:EBX.CLFLUSHOPT[bit 23] = 1).
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*/
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uint32_t reg[4];
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uint32_t leaf_7_ebx = 1 << 23; /* CLFLUSHOPT */
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/* check that leaf 7 is supported */
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raid_cpuid(0, 0, reg);
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if (reg[0] < 7)
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return 0;
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raid_cpuid(7, 0, reg);
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if ((reg[1] & leaf_7_ebx) != leaf_7_ebx)
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return 0;
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return 1;
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}
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static inline unsigned raid_cpu_clflush_size(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* CPUID - CPU Identification
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*
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* CPUID.01H:EBX.CLFLUSH[bits 15:8] reports the CLFLUSH cache-line
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* size in units of 8 bytes.
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*/
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uint32_t reg[4];
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raid_cpuid(1, 0, reg);
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return ((reg[1] >> 8) & 0xff) * 8;
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}
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static inline int raid_cpu_has_ssse3(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 12.7.2 Checking for SSSE3 Support
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* Before an application attempts to use the SSSE3 extensions, the application should
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* follow the steps illustrated in Section 11.6.2, "Checking for SSE/SSE2 Support."
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* Next, use the additional step provided below:
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* Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1).
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*/
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uint32_t leaf_1_ecx = 1 << 9; /* SSSE3 */
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uint32_t leaf_1_edx = 1 << 26; /* SSE2 */
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return raid_cpu_match_sse(leaf_1_ecx, leaf_1_edx);
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}
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static inline int raid_cpu_has_crc32(void)
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{
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/*
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* Intel 64 and IA-32 Architectures Software Developer's Manual
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* 325462-048US September 2013
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*
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* 12.12.3 Checking for SSE4.2 Support
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* ...
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* Before an application attempts to use the CRC32 instruction, it must check
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* that the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1).
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*/
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uint32_t leaf_1_ecx = 1 << 20; /* CRC32 */
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return raid_cpu_match_sse(leaf_1_ecx, 0);
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}
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static inline int raid_cpu_has_avx2(void)
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{
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/*
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* Intel Architecture Instruction Set Extensions Programming Reference
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* 319433-022 October 2014
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*
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* 14.3 Detection of AVX instructions
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* 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)
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* 2) Issue XGETBV and verify that XCR0[2:1] = `11b' (XMM state and YMM state are enabled by OS).
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* 3) detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
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* (Step 3 can be done in any order relative to 1 and 2)
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*
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* 14.7.1 Detection of AVX2
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* Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.
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* Application Software must identify that hardware supports AVX, after that it must
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* also detect support for AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5].
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*/
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uint32_t leaf_1_ecx = (1 << 27) | (1 << 28); /* XSAVE and AVX */
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uint32_t leaf_7_ebx = 1 << 5; /* AVX2 */
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uint32_t xcr0 = 3 << 1; /* OS saves XMM and YMM registers */
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return raid_cpu_match_avx(leaf_1_ecx, leaf_7_ebx, 0, xcr0);
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}
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static inline int raid_cpu_has_avx2gfni(void)
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{
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/*
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* Detection of AVX2 + GFNI:
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* 1) Verify OSXSAVE and XGETBV (CPUID.1:ECX[27])
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* 2) Verify XCR0[2:1] = '11b' (XMM and YMM state enabled)
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* 3) Verify AVX2 support (CPUID.7.0:EBX[5])
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* 4) Verify GFNI support (CPUID.7.0:ECX[8])
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*/
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uint32_t leaf_1_ecx = (1 << 27) | (1 << 28); /* XSAVE and AVX */
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uint32_t leaf_7_ebx = 1 << 5; /* AVX2 */
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uint32_t leaf_7_ecx = 1 << 8; /* GFNI */
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uint32_t xcr0 = 3 << 1; /* OS saves XMM and YMM registers */
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return raid_cpu_match_avx(leaf_1_ecx, leaf_7_ebx, leaf_7_ecx, xcr0);
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}
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static inline int raid_cpu_has_avx512bw(void)
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{
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/*
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* Intel Architecture Instruction Set Extensions Programming Reference
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* 319433-022 October 2014
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*
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* 2.2 Detection of 512-bit Instruction Groups of Intel AVX-512 Family
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* 1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use)
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* 2) Execute XGETBV and verify that XCR0[7:5] = `111b' (OPMASK state, upper 256-bit of
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* ZMM0-ZMM15 and ZMM16-ZMM31 state are enabled by OS) and that XCR0[2:1] = `11b'
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* (XMM state and YMM state are enabled by OS).
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* 3) Verify both CPUID.0x7.0:EBX.AVX512F[bit 16] = 1, CPUID.0x7.0:EBX.AVX512BW[bit 30] = 1.
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*/
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/*
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* Note that intentionally we don't check for AVX and AVX2
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* because the documentation doesn't require that
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*/
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uint32_t leaf_1_ecx = 1 << 27; /* XSAVE/XGETBV */
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uint32_t leaf_7_ebx = (1 << 16) | (1 << 30); /* AVX512F and AVX512BW */
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uint32_t xcr0 = (3 << 1) | (7 << 5); /* OS saves XMM, YMM and ZMM registers */
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return raid_cpu_match_avx(leaf_1_ecx, leaf_7_ebx, 0, xcr0);
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}
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static inline int raid_cpu_has_avx512gfni(void)
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{
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uint32_t leaf_1_ecx = 1 << 27; /* XSAVE/XGETBV */
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uint32_t leaf_7_ebx = (1 << 16) | (1 << 30); /* AVX512F and AVX512BW */
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uint32_t leaf_7_ecx = 1 << 8; /* GFNI */
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uint32_t xcr0 = (3 << 1) | (7 << 5); /* OS saves XMM, YMM and ZMM registers */
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return raid_cpu_match_avx(leaf_1_ecx, leaf_7_ebx, leaf_7_ecx, xcr0);
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}
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/**
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* Check if it's an Intel Atom CPU.
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*/
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static inline int raid_cpu_is_atom(unsigned family, unsigned model)
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{
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if (family != 6)
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return 0;
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/*
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* x86 Architecture CPUID
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* http://www.sandpile.org/x86/cpuid.htm
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*/
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switch (model) {
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case 28: /* 1C Atom (45 nm) */
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case 38: /* 26 Atom (45 nm) */
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case 39: /* 27 Atom (32 nm) */
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case 53: /* 35 Atom */
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case 54: /* 36 Atom (32 nm) */
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case 55: /* 37 Atom 4C (22 nm BYT) */
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case 74: /* 4A Atom 2C (22 nm TGR) */
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case 76: /* 4C Atom 4C (14 nm BSW) */
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case 77: /* 4D Atom 8C (22 nm AVN) */
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case 90: /* 5A Atom 4C (22 nm ANN) */
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case 93: /* 5D Atom 4C (28 nm SoFIA) */
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return 1;
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default:
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return 0;
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}
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}
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/**
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* Check if the processor has a slow MULT implementation.
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* If yes, it's better to use a hash not based on multiplication.
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*/
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static inline int raid_cpu_has_slowmult(void)
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{
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char vendor[CPU_VENDOR_MAX];
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unsigned family;
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unsigned model;
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/*
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* In some cases Murmur3 based on MUL instruction,
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* is a LOT slower than Spooky2 based on SHIFTs.
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*/
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raid_cpu_info(vendor, &family, &model);
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if (strcmp(vendor, "GenuineIntel") == 0) {
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/*
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* Intel Atom (Model 28)
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* murmur3:378 MB/s, spooky2:3413 MB/s (x86)
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*
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* Intel Atom (Model 77)
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* murmur3:1311 MB/s, spooky2:4056 MB/s (x64)
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*/
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if (raid_cpu_is_atom(family, model))
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return 1;
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}
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return 0;
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}
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/**
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* Check if the processor has a slow extended set of SSE registers.
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* If yes, it's better to limit the unrolling to the first 8 registers.
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*/
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static inline int raid_cpu_has_slow_extendedreg(void)
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{
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char vendor[CPU_VENDOR_MAX];
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unsigned family;
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unsigned model;
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/*
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* In some cases the PAR2 implementation using 16 SSE registers
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* is a LITTLE slower than the one using only the first 8 registers.
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* This doesn't happen for PARZ.
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*/
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raid_cpu_info(vendor, &family, &model);
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if (strcmp(vendor, "AuthenticAMD") == 0) {
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/*
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* AMD Bulldozer
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* par2_sse2:4922 MB/s, par2_sse2e:4465 MB/s
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*/
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if (family == 21)
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return 1;
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}
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if (strcmp(vendor, "GenuineIntel") == 0) {
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/*
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* Intel Atom (Model 77)
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* par2_sse2:5686 MB/s, par2_sse2e:5250 MB/s
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* parz_sse2:3100 MB/s, parz_sse2e:3400 MB/s
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* par3_sse3:1921 MB/s, par3_sse3e:1813 MB/s
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* par4_sse3:1175 MB/s, par4_sse3e:1113 MB/s
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* par5_sse3:876 MB/s, par5_sse3e:675 MB/s
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* par6_sse3:705 MB/s, par6_sse3e:529 MB/s
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*
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* Intel Atom (Model 77) "Avoton C2750"
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* par2_sse2:5661 MB/s, par2_sse2e:5382 MB/s
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* parz_sse2:3110 MB/s, parz_sse2e:3450 MB/s
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* par3_sse3:1769 MB/s, par3_sse3e:1856 MB/s
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* par4_sse3:1221 MB/s, par4_sse3e:1141 MB/s
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* par5_sse3:910 MB/s, par5_sse3e:675 MB/s
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* par6_sse3:720 MB/s, par6_sse3e:534 MB/s
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*/
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if (raid_cpu_is_atom(family, model))
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return 1;
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}
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return 0;
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}
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/*
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* Check if the processor has a "slow" AVX-512 implementation where a highly
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* optimized AVX-2 path will outperform the native AVX-512 path for this
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* specific parity kernel, which is dominated by vpshufb (AVX-512BW).
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*
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* Hardware condition causing this:
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*
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* Narrow Shuffle Port + Frequency Offset (Intel Skylake-X / Cannon Lake):
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* The shuffle execution port (port 5) on these cores is only 256-bit wide.
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* vpshufb zmm therefore decomposes into 2 µops through the same port,
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* delivering identical bytes-per-cycle throughput as vpshufb ymm, there
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* is zero computational gain from the wider register. On top of this, any
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* active 512-bit instruction triggers a core frequency downclocking license
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* (100-400 MHz under sustained load). The result is measurably worse
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* throughput than AVX-2 for this workload.
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* Note: Ice Lake, Tiger Lake, and Rocket Lake are intentionally excluded,
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* their port 5 is natively 512-bit wide (1 µop, genuine 2× vpshufb
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* throughput), which outweighs their smaller frequency offsets.
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*/
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static inline int raid_cpu_has_slow_avx512(void)
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{
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char vendor[CPU_VENDOR_MAX];
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unsigned family;
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unsigned model;
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raid_cpu_info(vendor, &family, &model);
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if (strcmp(vendor, "GenuineIntel") == 0) {
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/*
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* Skylake-X / Cascade Lake (0x55) and Cannon Lake (0x66).
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*
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* These have TWO compounding problems for vpshufb-heavy parity:
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*
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* 1. Port 5 (the shuffle port) is only 256-bit wide on these cores.
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* vpshufb zmm decomposes into 2 µops through the same port,
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* yielding identical bytes-per-cycle as vpshufb ymm.
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* There is zero throughput gain from the wider register.
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*
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* 2. Executing AVX-512 instructions triggers a frequency downclocking
|
||
* "license" (L0/L1 levels), reducing core frequency by 100-400 MHz
|
||
* under sustained 512-bit load.
|
||
*
|
||
* Ice Lake (0x7E, 0x6A, 0x6C), Tiger Lake (0x8C, 0x8D), and
|
||
* Rocket Lake (0xA7) are intentionally NOT listed: their port 5
|
||
* is natively 512-bit wide (1 µop, 2× throughput for vpshufb zmm),
|
||
* which outweighs their smaller frequency offsets.
|
||
*/
|
||
if (family == 6) {
|
||
if (model == 0x55 /* Skylake-X, Cascade Lake */
|
||
|| model == 0x66) /* Cannon Lake (rare) */
|
||
return 1;
|
||
}
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
#endif
|
||
|
||
#endif
|